lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <c2218911-650a-4f43-9119-bd2cfc46f3aa@quicinc.com>
Date: Mon, 12 Aug 2024 12:41:40 -0700
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
To: Stephen Boyd <swboyd@...omium.org>, Daniel Vetter <daniel@...ll.ch>,
        "David Airlie" <airlied@...il.com>,
        Dmitry Baryshkov
	<dmitry.baryshkov@...aro.org>,
        Marijn Suijten
	<marijn.suijten@...ainline.org>,
        Rob Clark <robdclark@...il.com>, Sean Paul
	<sean@...rly.run>,
        <freedreno@...ts.freedesktop.org>
CC: <dri-devel@...ts.freedesktop.org>, <quic_jesszhan@...cinc.com>,
        <dianders@...omium.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/msm: fix the highest_bank_bit for sc7180



On 8/12/2024 11:40 AM, Stephen Boyd wrote:
> Quoting Abhinav Kumar (2024-08-08 16:52:27)
>> sc7180 programs the ubwc settings as 0x1e as that would mean a
>> highest bank bit of 14 which matches what the GPU sets as well.
>>
>> However, the highest_bank_bit field of the msm_mdss_data which is
>> being used to program the SSPP's fetch configuration is programmed
>> to a highest bank bit of 16 as 0x3 translates to 16 and not 14.
>>
>> Fix the highest bank bit field used for the SSPP to match the mdss
>> and gpu settings.
>>
>> Fixes: 6f410b246209 ("drm/msm/mdss: populate missing data")
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
>> ---
>>   drivers/gpu/drm/msm/msm_mdss.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index d90b9471ba6f..faa88fd6eb4d 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -577,7 +577,7 @@ static const struct msm_mdss_data sc7180_data = {
>>          .ubwc_enc_version = UBWC_2_0,
>>          .ubwc_dec_version = UBWC_2_0,
>>          .ubwc_static = 0x1e,
>> -       .highest_bank_bit = 0x3,
>> +       .highest_bank_bit = 0x1,
> 
> Usually when I see hex it's because there's a mask. This isn't a mask
> though? Can it just be '1'?

I just retained the same convention that was used earlier. It seems like 
a mix and match right now. sc7180, sm6115 and qcm2290 were using 0x.

I can post a separate change to change all of them.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ