lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com>
Date: Mon, 12 Aug 2024 13:39:47 +0900
From: Kwanghoon Son <k.son@...sung.com>
To: Sunyeal Hong <sunyeal.hong@...sung.com>, Krzysztof Kozlowski
	<krzk@...nel.org>, Sylwester Nawrocki <s.nawrocki@...sung.com>, Chanwoo Choi
	<cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>, Michael
	Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob
	Herring <robh@...nel.org>,  Conor Dooley <conor+dt@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 4/4] clk: samsung: add top clock support for
 ExynosAuto v920 SoC

On Tue, 2024-07-30 at 16:12 +0900, Sunyeal Hong wrote:
> This adds support for CMU_TOP which generates clocks for all the
> function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For
> CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block
> and they will generate bus clocks.
> 
> Signed-off-by: Sunyeal Hong <sunyeal.hong@...sung.com>
> ---
>  drivers/clk/samsung/Makefile             |    1 +
>  drivers/clk/samsung/clk-exynosautov920.c | 1173 ++++++++++++++++++++++
>  2 files changed, 1174 insertions(+)
>  create mode 100644 drivers/clk/samsung/clk-exynosautov920.c
> 

[snip]

> +static const struct samsung_cmu_info peric0_cmu_info __initconst = {
> +	.mux_clks		= peric0_mux_clks,
> +	.nr_mux_clks		= ARRAY_SIZE(peric0_mux_clks),
> +	.div_clks		= peric0_div_clks,
> +	.nr_div_clks		= ARRAY_SIZE(peric0_div_clks),
> +	.nr_clk_ids		= CLKS_NR_PERIC0,
> +	.clk_regs		= peric0_clk_regs,
> +	.nr_clk_regs		= ARRAY_SIZE(peric0_clk_regs),
> +	.clk_name		= "dout_clkcmu_peric0_noc",

Maybe silly question, (I'm really new to this cmu).
Isn't it should be "noc"?

I thought this name is from dt binding.
(drivers/clk/samsung/clk-exynos-arm64.c)


		parent_clk = clk_get(dev, cmu->clk_name);
		data = dev_get_drvdata(dev);

That's why GS101, and my recent v9 patch name like "bus".

Best regards,
kwang.

> +};
> +
> +static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
> +{
> +	const struct samsung_cmu_info *info;
> +	struct device *dev = &pdev->dev;
> +
> +	info = of_device_get_match_data(dev);
> +	exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id exynosautov920_cmu_of_match[] = {
> +	{
> +		.compatible = "samsung,exynosautov920-cmu-peric0",
> +		.data = &peric0_cmu_info,
> +	},
> +};
> +
> +static struct platform_driver exynosautov920_cmu_driver __refdata = {
> +	.driver = {
> +		.name = "exynosautov920-cmu",
> +		.of_match_table = exynosautov920_cmu_of_match,
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe = exynosautov920_cmu_probe,
> +};
> +
> +static int __init exynosautov920_cmu_init(void)
> +{
> +	return platform_driver_register(&exynosautov920_cmu_driver);
> +}
> +core_initcall(exynosautov920_cmu_init);


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ