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Message-ID: <20240812114109.woyowj5en2ombx7h@deafening>
Date: Mon, 12 Aug 2024 06:41:09 -0500
From: Nishanth Menon <nm@...com>
To: Bryan Brattlof <bb@...com>
CC: Vignesh Raghavendra <vigneshr@...com>, Tero Kristo <kristo@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] arm64: dts: ti: k3-am62p: add opp frequencies
On 17:01-20240809, Bryan Brattlof wrote:
> Add OPP table for the am62px-sk allowing us to slow down CPUs when idle
Please fix the commit message. This is a device tree hardware
description. what the OS does with the frequencies is upto the OS.
Please also add documentation that provides the following information.
>
> Signed-off-by: Bryan Brattlof <bb@...com>
> ---
> .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 +++
> arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++
> arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 ++++++++++++++++++++++
> 3 files changed, 61 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> index 315d0092e7366..6f32135f00a55 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> @@ -20,6 +20,11 @@ chipid: chipid@14 {
> bootph-all;
> };
>
> + opp_efuse_table: syscon@18 {
> + compatible = "ti,am62-opp-efuse-table", "syscon";
> + reg = <0x18 0x4>;
> + };
> +
> cpsw_mac_syscon: ethernet-mac-syscon@200 {
> compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
> reg = <0x200 0x8>;
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> index ff65955551a32..ab5d7a5fc6118 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> @@ -128,6 +128,15 @@ led-0 {
> };
> };
>
> + opp-table {
> + /* Requires VDD_CORE at 0v85 */
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-supported-hw = <0x01 0x0004>;
> + clock-latency-ns = <6000000>;
> + };
> + };
> +
> tlv320_mclk: clk-0 {
> #clock-cells = <0>;
> compatible = "fixed-clock";
Please keep the board dts changes separate.
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> index 41f479dca4555..140587d02e88e 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> @@ -47,6 +47,7 @@ cpu0: cpu@0 {
> d-cache-line-size = <64>;
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> + operating-points-v2 = <&a53_opp_table>;
> clocks = <&k3_clks 135 0>;
> };
>
> @@ -62,6 +63,7 @@ cpu1: cpu@1 {
> d-cache-line-size = <64>;
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> + operating-points-v2 = <&a53_opp_table>;
> clocks = <&k3_clks 136 0>;
> };
>
> @@ -77,6 +79,7 @@ cpu2: cpu@2 {
> d-cache-line-size = <64>;
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> + operating-points-v2 = <&a53_opp_table>;
> clocks = <&k3_clks 137 0>;
> };
>
> @@ -92,10 +95,54 @@ cpu3: cpu@3 {
> d-cache-line-size = <64>;
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> + operating-points-v2 = <&a53_opp_table>;
> clocks = <&k3_clks 138 0>;
> };
> };
>
> + a53_opp_table: opp-table {
> + compatible = "operating-points-v2-ti-cpu";
> + opp-shared;
> + syscon = <&opp_efuse_table>;
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-supported-hw = <0x01 0x0007>;
> + clock-latency-ns = <6000000>;
> + };
> +
> + opp-400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-supported-hw = <0x01 0x0007>;
> + clock-latency-ns = <6000000>;
> + };
> +
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-supported-hw = <0x01 0x0007>;
> + clock-latency-ns = <6000000>;
> + };
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-supported-hw = <0x01 0x0007>;
> + clock-latency-ns = <6000000>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-supported-hw = <0x01 0x0006>;
> + clock-latency-ns = <6000000>;
> + };
> +
> + opp-1250000000 {
> + opp-hz = /bits/ 64 <1250000000>;
> + opp-supported-hw = <0x01 0x0004>;
> + clock-latency-ns = <6000000>;
> + opp-suspend;
> + };
> + };
> +
> l2_0: l2-cache0 {
> compatible = "cache";
> cache-unified;
>
> --
> 2.45.2
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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