linux-kernel - Re: [PATCH 3/3] cxl: Avoid to create dax regions for type2 accelerators

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Message-ID: <01ca9abf-45b0-90c1-d503-5e53eb4904c4@amd.com>
Date: Mon, 12 Aug 2024 12:50:04 +0100
From: Alejandro Lucero Palau <alucerop@....com>
To: "Huang, Ying" <ying.huang@...el.com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>
Cc: Dan Williams <dan.j.williams@...el.com>, Dave Jiang
 <dave.jiang@...el.com>, linux-cxl@...r.kernel.org,
 linux-kernel@...r.kernel.org, Davidlohr Bueso <dave@...olabs.net>,
 Alison Schofield <alison.schofield@...el.com>,
 Vishal Verma <vishal.l.verma@...el.com>, Ira Weiny <ira.weiny@...el.com>
Subject: Re: [PATCH 3/3] cxl: Avoid to create dax regions for type2
 accelerators

I do not understand why you took this change from my patchset.

Maybe the other two patches have a pass, but this should not be removed 
from my patchset, not at least after discussing it publicly.

The reason you mentioned for doing it was for making things easier for 
the other changes in my larger patchset, but again, you should have 
discussed this first publicly, and second, I do not remember other large 
patchsets, far larger than mine, being partially picked up  by someone 
else but the patchset submitter, and sending those picked changes in 
another patchset.


On 8/6/24 06:52, Huang, Ying wrote:
> Jonathan Cameron <Jonathan.Cameron@...wei.com> writes:
>
>> On Mon, 29 Jul 2024 16:46:11 +0800
>> Huang Ying <ying.huang@...el.com> wrote:
>>
>>> The memory range of a type2 accelerator should be managed by the type2
>>> accelerator specific driver instead of the common dax region drivers,
>>> as discussed in [1].
>>>
>>> [1] https://lore.kernel.org/linux-cxl/66469ff1b8fbc_2c2629427@dwillia2-xfh.jf.intel.com.notmuch/
>>>
>>> So, in this patch, we skip dax regions creation for type2 accelerator
>>> device memory regions.
>>>
>>> Based on: https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/
>>>
>>> Signed-off-by: "Huang, Ying" <ying.huang@...el.com>
>>> Co-developed-by: Dan Williams <dan.j.williams@...el.com>
>>> Signed-off-by: Dan Williams <dan.j.williams@...el.com>
>>> Cc: Davidlohr Bueso <dave@...olabs.net>
>>> Cc: Jonathan Cameron <jonathan.cameron@...wei.com>
>>> Cc: Dave Jiang <dave.jiang@...el.com>
>>> Cc: Alison Schofield <alison.schofield@...el.com>
>>> Cc: Vishal Verma <vishal.l.verma@...el.com>
>>> Cc: Ira Weiny <ira.weiny@...el.com>
>>> Cc: Alejandro Lucero <alucerop@....com>
>>> ---
>>>   drivers/cxl/core/region.c | 8 ++++++++
>>>   1 file changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>>> index 9a483c8a32fd..b37e12bb4a35 100644
>>> --- a/drivers/cxl/core/region.c
>>> +++ b/drivers/cxl/core/region.c
>>> @@ -3435,6 +3435,14 @@ static int cxl_region_probe(struct device *dev)
>>>   					p->res->start, p->res->end, cxlr,
>>>   					is_system_ram) > 0)
>>>   			return 0;
>>> +		/*
>>> +		 * HDM-D[B] (device-memory) regions have accelerator
>>> +		 * specific usage, skip device-dax registration.
>>> +		 */
>>> +		if (cxlr->type == CXL_DECODER_DEVMEM)
>>> +			return 0;
>> As in previous need to be careful as that may not mean it's
>> an accelerator.
> Yes.  We need some other way to identify type2 devices.
>
>> However, we do need to deal with BI setup for HDM-DB type 3 devices
>> etc and to check the HDM Decoder capability registers to make sure
>> Supported Coherence model is appropriate. (e.g. 11 for host only or
>> device coherency - HDM-H/HDM-DB)
> Yes.  We need to check BI configuration too.
>
>>> +
>>> +		/* HDM-H routes to device-dax */
>>>   		return devm_cxl_add_dax_region(cxlr);
>>>   	default:
>>>   		dev_dbg(&cxlr->dev, "unsupported region mode: %d\n",
> --
> Best Regards,
> Huang, Ying