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Message-ID: <20240812120529.3564390-3-christian.bruel@foss.st.com>
Date: Mon, 12 Aug 2024 14:05:26 +0200
From: Christian Bruel <christian.bruel@...s.st.com>
To: <vkoul@...nel.org>, <kishon@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<mcoquelin.stm32@...il.com>, <alexandre.torgue@...s.st.com>,
<p.zabel@...gutronix.de>
CC: <linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<fabrice.gasnier@...s.st.com>,
Christian Bruel <christian.bruel@...s.st.com>
Subject: [PATCH 2/5] dt-bindings: phy: Add STM32MP25 COMBOPHY bindings
Document the bindings for STM32 COMBOPHY interface, used to support
the PCIe and USB3 stm32mp25 drivers.
Following entries can be used to tune caracterisation parameters
- st,output-micro-ohms and st,output-vswing-microvolt bindings entries
to tune the impedance and voltage swing using discrete simulation results
- st, phy_rx0_eq register to set the internal rx equalizer filter value.
Signed-off-by: Christian Bruel <christian.bruel@...s.st.com>
---
.../bindings/phy/st,stm32-combophy.yaml | 178 ++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml
diff --git a/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml
new file mode 100644
index 0000000000000..6a53ab834b2a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/st,stm32-combophy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY
+
+maintainers:
+ - Christian Bruel <christian.bruel@...s.st.com>
+
+description: |
+ Single lane PHY shared (exclusive) between the USB3 and PCIe controllers.
+ Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1.
+
+properties:
+ compatible:
+ const: st,stm32mp25-combophy
+
+ reg:
+ maxItems: 1
+
+ st,syscfg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: Phandle to the SYSCON entry required for configuring PCIe
+ or USB3.
+
+ "#phy-cells":
+ const: 1
+ description: |
+ The cells contain the following arguments.
+
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_USB3
+ - PHY_TYPE_PCIE
+
+ clocks:
+ anyOf:
+ - description: apb-clk Bus clock mandatory to access registers.
+ - description: ker-clk Internal RCC reference clock for USB3 or PCIe
+ - description: pad-clk Optional on board clock input for PCIe only. Typically an
+ external 100Mhz oscillator wired on dedicated CLKIN pad. Used as reference
+ clock input instead of the ker-clk
+
+ clock-names:
+ oneOf:
+ - items:
+ - const: apb-clk
+ - const: ker-clk
+
+ - items:
+ - const: apb-clk
+ - const: ker-clk
+ - const: pad-clk
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: phy-rst
+
+ power-domains:
+ maxItems: 1
+
+ st,ssc-on:
+ type: boolean
+ description:
+ A boolean property whose presence indicates that the SSC for common clock
+ needs to be set.
+
+ st,rx_equalizer:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ default: 2
+ description:
+ A 3 bit value describing internal filter settings for the RX equalizer.
+
+ st,output-micro-ohms:
+ minimum: 3999000
+ maximum: 6090000
+ default: 4968000
+ description:
+ A value property to tune the Single Ended Output Impedance, simulations results
+ at 25C for a VDDP=0.8V. The hardware accepts discrete values in this range.
+
+ st,output-vswing-microvolt:
+ minimum: 442000
+ maximum: 803000
+ default: 803000
+ description:
+ A value property in microvolt to tune the Single Ended Output Voltage Swing to change the
+ Vlo, Vhi for a VDDP = 0.8V. The hardware accepts discrete values in this range.
+
+ wakeup-source: true
+
+ interrupts:
+ maxItems: 1
+ description: interrupt used for wakeup
+
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - st,syscfg
+ - '#phy-cells'
+ - resets
+ - reset-names
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ required:
+ - wakeup-source
+ then:
+ anyOf:
+ - required: [interrupts]
+ - required: [interrupts-extended]
+
+additionalProperties: false
+
+examples:
+ - |
+ // Example 1: COMBOPHY configured to use internal reference clock
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/st,stm32mp25-rcc.h>
+
+ combophy_internal: phy@...c0000 {
+ compatible = "st,stm32mp25-combophy";
+ reg = <0x480c0000 0x1000>;
+ #phy-cells = <1>;
+ clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
+ clock-names = "apb-clk", "ker-clk";
+ resets = <&rcc USB3PCIEPHY_R>;
+ reset-names = "phy-rst";
+ st,syscfg = <&syscfg>;
+ access-controllers = <&rifsc 67>;
+ power-domains = <&CLUSTER_PD>;
+ wakeup-source;
+ interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ - |
+ // Example 2: COMBOPHY configured to use extrenal 100MHz reference clock
+ // on CLKIN pad for PCIe
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/st,stm32mp25-rcc.h>
+
+ clocks {
+ pad_clk: pad-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ };
+
+ combophy_pad: phy@...c0000 {
+ compatible = "st,stm32mp25-combophy";
+ reg = <0x480c0000 0x1000>;
+ #phy-cells = <1>;
+ clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_clk>;
+ clock-names = "apb-clk", "ker-clk", "pad-clk";
+ resets = <&rcc USB3PCIEPHY_R>;
+ reset-names = "phy-rst";
+ st,syscfg = <&syscfg>;
+ access-controllers = <&rifsc 67>;
+ power-domains = <&CLUSTER_PD>;
+ wakeup-source;
+ interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
+ };
+...
--
2.34.1
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