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Message-ID:
<TY3PR01MB11346E95ED1171818488EFEFA86852@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Mon, 12 Aug 2024 12:25:48 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Prabhakar <prabhakar.csengg@...il.com>, Geert Uytterhoeven
<geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>
CC: "linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Fabrizio
Castro <fabrizio.castro.jz@...esas.com>, Prabhakar Mahadev Lad
<prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3
nodes
Hi Prabhakar,
> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@...il.com>
> Sent: Sunday, August 11, 2024 9:50 PM
> Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v1->v2
> - New patch
> ---
> arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> index 435b1f4e7d38..7f4e8ad9b0a5 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -184,6 +184,17 @@ scif: serial@...01400 {
> status = "disabled";
> };
>
> + wdt0: watchdog@...00400 {
> + compatible = "renesas,r9a09g057-wdt";
> + reg = <0 0x11c00400 0 0x400>;
> + clocks = <&cpg CPG_MOD 75>,
> + <&cpg CPG_MOD 76>;
> + clock-names = "pclk", "oscclk";
> + resets = <&cpg 117>;
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> ostm4: timer@...00000 {
> compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> reg = <0x0 0x12c00000 0x0 0x1000>;
> @@ -224,6 +235,28 @@ ostm7: timer@...03000 {
> status = "disabled";
> };
>
> + wdt2: watchdog@...00000 {
> + compatible = "renesas,r9a09g057-wdt";
> + reg = <0 0x13000000 0 0x400>;
> + clocks = <&cpg CPG_MOD 79>,
> + <&cpg CPG_MOD 80>;
> + clock-names = "pclk", "oscclk";
> + resets = <&cpg 119>;
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
I guess same group(all wdt together) arranged together?? Not sure.
Cheers,
Biju
> +
> + wdt3: watchdog@...00400 {
> + compatible = "renesas,r9a09g057-wdt";
> + reg = <0 0x13000400 0 0x400>;
> + clocks = <&cpg CPG_MOD 81>,
> + <&cpg CPG_MOD 82>;
> + clock-names = "pclk", "oscclk";
> + resets = <&cpg 120>;
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> ostm2: timer@...00000 {
> compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> reg = <0x0 0x14000000 0x0 0x1000>;
> @@ -244,6 +277,17 @@ ostm3: timer@...01000 {
> status = "disabled";
> };
>
> + wdt1: watchdog@...00000 {
> + compatible = "renesas,r9a09g057-wdt";
> + reg = <0 0x14400000 0 0x400>;
> + clocks = <&cpg CPG_MOD 77>,
> + <&cpg CPG_MOD 78>;
> + clock-names = "pclk", "oscclk";
> + resets = <&cpg 118>;
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> i2c0: i2c@...00400 {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.34.1
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