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Message-ID: <20240813104039.429b9fe6@canb.auug.org.au>
Date: Tue, 13 Aug 2024 10:40:39 +1000
From: Stephen Rothwell <sfr@...b.auug.org.au>
To: David Miller <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>
Cc: Networking <netdev@...r.kernel.org>, Linux Kernel Mailing List
<linux-kernel@...r.kernel.org>, Linux Next Mailing List
<linux-next@...r.kernel.org>, Pawel Dembicki <paweldembicki@...il.com>
Subject: linux-next: manual merge of the net-next tree with the net tree
Hi all,
Today's linux-next merge of the net-next tree got a conflict in:
drivers/net/dsa/vitesse-vsc73xx-core.c
between commits:
5b9eebc2c7a5 ("net: dsa: vsc73xx: pass value in phy_write operation")
fa63c6434b6f ("net: dsa: vsc73xx: check busy flag in MDIO operations")
from the net tree and commit:
2524d6c28bdc ("net: dsa: vsc73xx: use defined values in phy operations")
from the net-next tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/net/dsa/vitesse-vsc73xx-core.c
index e3f95d2cc2c1,a82b550a9e40..000000000000
--- a/drivers/net/dsa/vitesse-vsc73xx-core.c
+++ b/drivers/net/dsa/vitesse-vsc73xx-core.c
@@@ -225,12 -226,28 +226,30 @@@
#define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3
/* MII block 3 registers */
- #define VSC73XX_MII_STAT 0x0
- #define VSC73XX_MII_CMD 0x1
- #define VSC73XX_MII_DATA 0x2
+ #define VSC73XX_MII_STAT 0x0
+ #define VSC73XX_MII_CMD 0x1
+ #define VSC73XX_MII_DATA 0x2
+ #define VSC73XX_MII_MPRES 0x3
+
+ #define VSC73XX_MII_STAT_BUSY BIT(3)
+ #define VSC73XX_MII_STAT_READ BIT(2)
+ #define VSC73XX_MII_STAT_WRITE BIT(1)
+
+ #define VSC73XX_MII_CMD_SCAN BIT(27)
+ #define VSC73XX_MII_CMD_OPERATION BIT(26)
+ #define VSC73XX_MII_CMD_PHY_ADDR GENMASK(25, 21)
+ #define VSC73XX_MII_CMD_PHY_REG GENMASK(20, 16)
+ #define VSC73XX_MII_CMD_WRITE_DATA GENMASK(15, 0)
+
+ #define VSC73XX_MII_DATA_FAILURE BIT(16)
+ #define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0)
+
+ #define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6)
+ #define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0)
+ #define VSC73XX_MII_PRESCALEVAL_MIN 3 /* min allowed mdio clock prescaler */
+#define VSC73XX_MII_STAT_BUSY BIT(3)
+
/* Arbiter block 5 registers */
#define VSC73XX_ARBEMPTY 0x0c
#define VSC73XX_ARBDISC 0x0e
@@@ -557,24 -557,20 +576,28 @@@ static int vsc73xx_phy_read(struct dsa_
u32 val;
int ret;
+ ret = vsc73xx_mdio_busy_check(vsc);
+ if (ret)
+ return ret;
+
/* Setting bit 26 means "read" */
- cmd = BIT(26) | (phy << 21) | (regnum << 16);
- ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd);
+ cmd = VSC73XX_MII_CMD_OPERATION |
+ FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) |
+ FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum);
+ ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
+ VSC73XX_MII_CMD, cmd);
if (ret)
return ret;
- msleep(2);
+
+ ret = vsc73xx_mdio_busy_check(vsc);
+ if (ret)
+ return ret;
+
- ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val);
+ ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
+ VSC73XX_MII_DATA, &val);
if (ret)
return ret;
- if (val & BIT(16)) {
+ if (val & VSC73XX_MII_DATA_FAILURE) {
dev_err(vsc->dev, "reading reg %02x from phy%d failed\n",
regnum, phy);
return -EIO;
@@@ -594,12 -590,21 +617,14 @@@ static int vsc73xx_phy_write(struct dsa
u32 cmd;
int ret;
- /* It was found through tedious experiments that this router
- * chip really hates to have it's PHYs reset. They
- * never recover if that happens: autonegotiation stops
- * working after a reset. Just filter out this command.
- * (Resetting the whole chip is OK.)
- */
- if (regnum == 0 && (val & BIT(15))) {
- dev_info(vsc->dev, "reset PHY - disallowed\n");
- return 0;
- }
+ ret = vsc73xx_mdio_busy_check(vsc);
+ if (ret)
+ return ret;
- cmd = (phy << 21) | (regnum << 16) | val;
- ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd);
+ cmd = FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) |
- FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum);
++ FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum) | val;
+ ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
+ VSC73XX_MII_CMD, cmd);
if (ret)
return ret;
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