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Message-ID: <CAJgzZopz0SpWn7tEBctG+qEcgF829Zes8-6U=ZEAriZagaB80w@mail.gmail.com>
Date: Tue, 13 Aug 2024 14:03:44 -0400
From: enh <enh@...gle.com>
To: Charlie Jenkins <charlie@...osinc.com>
Cc: Evan Green <evan@...osinc.com>, Palmer Dabbelt <palmer@...belt.com>,
Yangyu Chen <cyy@...self.name>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alexghiti@...osinc.com>, Andrew Jones <ajones@...tanamicro.com>,
Andy Chiu <andy.chiu@...ive.com>, Ben Dooks <ben.dooks@...ethink.co.uk>,
Björn Töpel <bjorn@...osinc.com>,
Clément Léger <cleger@...osinc.com>,
Conor Dooley <conor.dooley@...rochip.com>, Costa Shulyupin <costa.shul@...hat.com>,
Erick Archer <erick.archer@....com>, "Gustavo A. R. Silva" <gustavoars@...nel.org>,
Jonathan Corbet <corbet@....net>, Paul Walmsley <paul.walmsley@...ive.com>, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v4 2/2] RISC-V: hwprobe: Add SCALAR to misaligned perf defines
On Fri, Aug 9, 2024 at 5:57 PM Charlie Jenkins <charlie@...osinc.com> wrote:
>
> On Fri, Aug 09, 2024 at 02:44:44PM -0700, Evan Green wrote:
> > In preparation for misaligned vector performance hwprobe keys, rename
> > the hwprobe key values associated with misaligned scalar accesses to
> > include the term SCALAR. Leave the old defines in place to maintain
> > source compatibility.
> >
> > This change is intended to be a functional no-op.
> >
> > Signed-off-by: Evan Green <evan@...osinc.com>
> > Reviewed-by: Charlie Jenkins <charlie@...osinc.com>
> >
> > ---
> >
> > Changes in v4:
> > - Add the word scalar (Charlie)
> >
> > Changes in v3:
> > - Leave the old defines in place (Conor, Palmer)
> >
> > Changes in v2:
> > - Added patch to rename misaligned perf key values (Palmer)
> >
> > Documentation/arch/riscv/hwprobe.rst | 28 ++++++++++++----------
> > arch/riscv/include/uapi/asm/hwprobe.h | 5 ++++
> > arch/riscv/kernel/sys_hwprobe.c | 10 ++++----
> > arch/riscv/kernel/traps_misaligned.c | 6 ++---
> > arch/riscv/kernel/unaligned_access_speed.c | 12 +++++-----
> > 5 files changed, 34 insertions(+), 27 deletions(-)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index a994eed75bde..85b709257918 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -247,23 +247,25 @@ The following keys are defined:
> > the performance of misaligned scalar native word accesses on the selected set
> > of processors.
> >
> > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned
> > - accesses is unknown.
> > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of
> > + misaligned scalar accesses is unknown.
>
> + enh <enh@...gle.com>
>
> Thanks for respinning this Evan! With this wording change the patch that
> changes the wording but not the macro [1] is no longer needed.
yeah, this is much better. thanks!
> - Charlie
>
> Link:
> https://lore.kernel.org/linux-riscv/CAJgzZorn5anPH8dVPqvjVWmLKqTi5bkLDR=FH-ZAcdXFnNe8Eg@mail.gmail.com/
> [1]
>
> >
> > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are
> > - emulated via software, either in or below the kernel. These accesses are
> > - always extremely slow.
> > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar
> > + accesses are emulated via software, either in or below the kernel. These
> > + accesses are always extremely slow.
> >
> > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned native word
> > - sized accesses are slower than the equivalent quantity of byte accesses.
> > - Misaligned accesses may be supported directly in hardware, or trapped and
> > - emulated by software.
> > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native
> > + word sized accesses are slower than the equivalent quantity of byte
> > + accesses. Misaligned accesses may be supported directly in hardware, or
> > + trapped and emulated by software.
> >
> > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned native word
> > - sized accesses are faster than the equivalent quantity of byte accesses.
> > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native
> > + word sized accesses are faster than the equivalent quantity of byte
> > + accesses.
> >
> > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
> > - not supported at all and will generate a misaligned address fault.
> > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar
> > + accesses are not supported at all and will generate a misaligned address
> > + fault.
> >
> > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
> > represents the size of the Zicboz block in bytes.
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 635753084275..1e153cda57db 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -83,6 +83,11 @@ struct riscv_hwprobe {
> > #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7
> > #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8
> > #define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF 9
> > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0
> > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1
> > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2
> > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3
> > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4
> > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
> >
> > /* Flags */
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index 2d0f4f6a32c3..cea0ca2bf2a2 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -178,13 +178,13 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > perf = this_perf;
> >
> > if (perf != this_perf) {
> > - perf = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
> > + perf = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;
> > break;
> > }
> > }
> >
> > if (perf == -1ULL)
> > - return RISCV_HWPROBE_MISALIGNED_UNKNOWN;
> > + return RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;
> >
> > return perf;
> > }
> > @@ -192,12 +192,12 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > {
> > if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS))
> > - return RISCV_HWPROBE_MISALIGNED_FAST;
> > + return RISCV_HWPROBE_MISALIGNED_SCALAR_FAST;
> >
> > if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available())
> > - return RISCV_HWPROBE_MISALIGNED_EMULATED;
> > + return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;
> >
> > - return RISCV_HWPROBE_MISALIGNED_SLOW;
> > + return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW;
> > }
> > #endif
> >
> > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> > index b62d5a2f4541..192cd5603e95 100644
> > --- a/arch/riscv/kernel/traps_misaligned.c
> > +++ b/arch/riscv/kernel/traps_misaligned.c
> > @@ -338,7 +338,7 @@ int handle_misaligned_load(struct pt_regs *regs)
> > perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
> >
> > #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
> > - *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED;
> > + *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;
> > #endif
> >
> > if (!unaligned_enabled)
> > @@ -532,13 +532,13 @@ static bool check_unaligned_access_emulated(int cpu)
> > unsigned long tmp_var, tmp_val;
> > bool misaligned_emu_detected;
> >
> > - *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
> > + *mas_ptr = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;
> >
> > __asm__ __volatile__ (
> > " "REG_L" %[tmp], 1(%[ptr])\n"
> > : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");
> >
> > - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);
> > + misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED);
> > /*
> > * If unaligned_ctl is already set, this means that we detected that all
> > * CPUS uses emulated misaligned access at boot time. If that changed
> > diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
> > index a9a6bcb02acf..160628a2116d 100644
> > --- a/arch/riscv/kernel/unaligned_access_speed.c
> > +++ b/arch/riscv/kernel/unaligned_access_speed.c
> > @@ -34,9 +34,9 @@ static int check_unaligned_access(void *param)
> > struct page *page = param;
> > void *dst;
> > void *src;
> > - long speed = RISCV_HWPROBE_MISALIGNED_SLOW;
> > + long speed = RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW;
> >
> > - if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN)
> > + if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN)
> > return 0;
> >
> > /* Make an unaligned destination buffer. */
> > @@ -95,14 +95,14 @@ static int check_unaligned_access(void *param)
> > }
> >
> > if (word_cycles < byte_cycles)
> > - speed = RISCV_HWPROBE_MISALIGNED_FAST;
> > + speed = RISCV_HWPROBE_MISALIGNED_SCALAR_FAST;
> >
> > ratio = div_u64((byte_cycles * 100), word_cycles);
> > pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.%02d, unaligned accesses are %s\n",
> > cpu,
> > ratio / 100,
> > ratio % 100,
> > - (speed == RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow");
> > + (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) ? "fast" : "slow");
> >
> > per_cpu(misaligned_access_speed, cpu) = speed;
> >
> > @@ -110,7 +110,7 @@ static int check_unaligned_access(void *param)
> > * Set the value of fast_misaligned_access of a CPU. These operations
> > * are atomic to avoid race conditions.
> > */
> > - if (speed == RISCV_HWPROBE_MISALIGNED_FAST)
> > + if (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST)
> > cpumask_set_cpu(cpu, &fast_misaligned_access);
> > else
> > cpumask_clear_cpu(cpu, &fast_misaligned_access);
> > @@ -188,7 +188,7 @@ static int riscv_online_cpu(unsigned int cpu)
> > static struct page *buf;
> >
> > /* We are already set since the last check */
> > - if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN)
> > + if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN)
> > goto exit;
> >
> > buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER);
> > --
> > 2.34.1
> >
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