linux-kernel - Re: [PATCH v2 07/36] dt-bindings: soc: fsl: cpm

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Message-ID: <172357568355.1494768.17469941704094420222.robh@kernel.org>
Date: Tue, 13 Aug 2024 13:01:24 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Herve Codina <herve.codina@...tlin.com>
Cc: devicetree@...r.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
	Conor Dooley <conor+dt@...nel.org>, Mark Brown <broonie@...nel.org>,
	linux-kernel@...r.kernel.org, Li Yang <leoyang.li@....com>,
	Christophe Leroy <christophe.leroy@...roup.eu>,
	Qiang Zhao <qiang.zhao@....com>, linuxppc-dev@...ts.ozlabs.org,
	linux-arm-kernel@...ts.infradead.org,
	Krzysztof Kozlowski <krzk+dt@...nel.org>
Subject: Re: [PATCH v2 07/36] dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine
 (QE) TSA controller


On Thu, 08 Aug 2024 09:11:00 +0200, Herve Codina wrote:
> Add support for the time slot assigner (TSA) available in some
> PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
> 
> This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
> Communication Controllers) instead of SCCs (Serial Communication
> Controllers). Also, compared against the CPM TSA, this QE TSA can handle
> up to 4 TDMs instead of 2 and allows to configure the logic level of
> sync signals.
> 
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
> ---
>  .../bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml   | 210 ++++++++++++++++++
>  include/dt-bindings/soc/qe-fsl,tsa.h          |  13 ++
>  2 files changed, 223 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml
>  create mode 100644 include/dt-bindings/soc/qe-fsl,tsa.h
> 

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>