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Message-ID: <147572ea-c5ae-7992-6015-3181f10a785e@gentwo.org>
Date: Tue, 13 Aug 2024 12:41:11 -0700 (PDT)
From: "Christoph Lameter (Ampere)" <cl@...two.org>
To: Waiman Long <longman@...hat.com>
cc: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, 
    Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>, 
    Boqun Feng <boqun.feng@...il.com>, 
    Linus Torvalds <torvalds@...ux-foundation.org>, linux-mm@...ck.org, 
    linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH RFC] Avoid memory barrier in read_seqcount() through load
 acquire

On Tue, 13 Aug 2024, Waiman Long wrote:

> Do we need a new ARCH flag? I believe barrier APIs like smp_load_acquire() 
> will use the full barrier for those arch'es that don't define their own 
> smp_load_acquire().

Well this is a load acquire instruction. The fallback of smp_load_aquire 
is:

#define __smp_load_acquire(p)                                           \
({                                                                      \
         __unqual_scalar_typeof(*p) ___p1 = READ_ONCE(*p);               \
         compiletime_assert_atomic_type(*p);                             \
         __smp_mb();                                                     \
         (typeof(*p))___p1;                                              \
})

Looks like we have an acquire + barrier here.

> BTW, acquire/release can be considered memory barriers too. Maybe you are 
> talking about preferring acquire/release barriers over read/write barriers. 
> Right?

Load acquire is a single instruction load that does not require full 
barrier semantics for the critical section but ensures that the value is 
loaded before all following. Regular barriers do not have this singe load 
that isolates the critical section and sequence all loads around them.


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