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Message-ID: <20240814194937.1868-2-thorsten.blum@toblux.com>
Date: Wed, 14 Aug 2024 21:49:38 +0200
From: Thorsten Blum <thorsten.blum@...lux.com>
To: dinguyen@...nel.org,
mturquette@...libre.com,
sboyd@...nel.org
Cc: linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Thorsten Blum <thorsten.blum@...lux.com>
Subject: [PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
Since readl() returns a u32, the local variable reg can also have the
data type u32. Furthermore, divf and divq are derived from reg and can
also be a u32.
Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:
WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
Compile-tested only.
Signed-off-by: Thorsten Blum <thorsten.blum@...lux.com>
---
drivers/clk/socfpga/clk-pll-a10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index b028f25c658a..62eed964c3d0 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -35,7 +35,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
- unsigned long divf, divq, reg;
+ u32 divf, divq, reg;
unsigned long long vco_freq;
/* read VCO1 reg for numerator and denominator */
--
2.45.2
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