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Message-ID: <20240814-b4-upstream-bootph-all-v4-1-f2b462000f25@ti.com>
Date: Wed, 14 Aug 2024 13:17:28 +0530
From: Manorit Chawdhry <m-chawdhry@...com>
To: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Tero
Kristo <kristo@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof
Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: <linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, Neha Malcom Francis <n-francis@...com>,
Aniket Limaye <a-limaye@...com>, Udit Kumar <u-kumar1@...com>,
Beleswar Padhi
<b-padhi@...com>,
Siddharth Vadapalli <s-vadapalli@...com>, Andrew Davis
<afd@...com>,
Manorit Chawdhry <m-chawdhry@...com>
Subject: [PATCH v4 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Reviewed-by: Andrew Davis <afd@...com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@...com>
---
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 4 +++-
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 17 +++++++++++++++--
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 2 ++
4 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index c5a0b7cbb14f..3b5f8f08cf32 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
+ bootph-all;
};
main_i2c3_pins_default: main-i2c3-default-pins {
@@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
+ bootph-all;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
+ bootph-all;
};
main_mcan3_pins_default: main-mcan3-default-pins {
@@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
+ bootph-all;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
@@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
+ bootph-all;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
+ bootph-all;
};
};
@@ -316,12 +322,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart8 {
@@ -330,6 +338,7 @@ &main_uart8 {
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+ bootph-all;
};
&main_i2c0 {
@@ -385,6 +394,7 @@ &main_sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&main_sdhci1 {
@@ -395,6 +405,7 @@ &main_sdhci1 {
disable-wp;
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
+ bootph-all;
};
&mcu_cpsw {
@@ -444,6 +455,7 @@ &usbss0 {
status = "okay";
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
+ bootph-all;
ti,vbus-divider;
ti,usb2-only;
};
@@ -451,6 +463,7 @@ &usbss0 {
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
+ bootph-all;
};
&ospi1 {
@@ -464,6 +477,7 @@ flash@0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
+ bootph-all;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 9ed6949b40e9..0d72dd0b5033 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -816,6 +816,7 @@ secure_proxy_main: mailbox@...00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};
hwspinlock: spinlock@...00000 {
@@ -1225,6 +1226,7 @@ usb0: usb@...0000 {
interrupt-names = "host", "peripheral", "otg";
maximum-speed = "super-speed";
dr_mode = "otg";
+ bootph-all;
};
};
@@ -1944,8 +1946,8 @@ c71_1: dsp@...00000 {
main_esm: esm@...000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x700000 0x00 0x1000>;
- ti,esm-pins = <688>, <689>;
bootph-pre-ram;
+ ti,esm-pins = <688>, <689>;
};
watchdog0: watchdog@...0000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 8feb42c89e47..05a5e35fddcd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ sms: system-controller@...83000 {
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};
@@ -43,6 +46,7 @@ wkup_conf: bus@...00000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};
@@ -53,6 +57,8 @@ secure_proxy_sa3: mailbox@...00000 {
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
+ bootph-pre-ram;
+
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
@@ -167,6 +173,7 @@ mcu_timer0: timer@...00000 {
assigned-clocks = <&k3_clks 35 1>;
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ bootph-pre-ram;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
@@ -361,6 +368,7 @@ wkup_i2c0: i2c@...20000 {
clocks = <&k3_clks 223 1>;
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
+ bootph-all;
status = "disabled";
};
@@ -469,6 +477,7 @@ mcu_ringacc: ringacc@...00000 {
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ bootph-all;
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
@@ -488,6 +497,7 @@ mcu_udmap: dma-controller@...c0000 {
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
+ bootph-all;
ti,sci = <&sms>;
ti,sci-dev-id = <273>;
@@ -507,6 +517,8 @@ secure_proxy_mcu: mailbox@...80000 {
reg = <0x00 0x2a480000 0x00 0x80000>,
<0x00 0x2a380000 0x00 0x80000>,
<0x00 0x2a400000 0x00 0x80000>;
+ bootph-pre-ram;
+
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
@@ -667,6 +679,7 @@ wkup_vtm0: temperature-sensor@...40000 {
<0x00 0x42050000 0x0 0x350>;
power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
+ bootph-pre-ram;
};
mcu_r5fss0: r5fss@...00000 {
@@ -712,15 +725,15 @@ mcu_r5fss0_core1: r5f@...00000 {
mcu_esm: esm@...00000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
- ti,esm-pins = <95>;
bootph-pre-ram;
+ ti,esm-pins = <95>;
};
wkup_esm: esm@...80000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x42080000 0x00 0x1000>;
- ti,esm-pins = <63>;
bootph-pre-ram;
+ ti,esm-pins = <63>;
};
/*
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 36136db26a47..c333148f2789 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
>;
+ bootph-all;
};
};
@@ -440,6 +441,7 @@ flash@0 {
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
+ bootph-all;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
--
2.46.0
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