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Message-Id: <20240815055732.25252-1-mattc@purestorage.com>
Date: Wed, 14 Aug 2024 23:57:32 -0600
From: Matthew W Carlis <mattc@...estorage.com>
To: macro@...am.me.uk
Cc: bhelgaas@...gle.com,
ilpo.jarvinen@...ux.intel.com,
linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org,
mattc@...estorage.com,
mika.westerberg@...ux.intel.com,
oohall@...il.com
Subject: Re: [PATCH v2 2/4] PCI: Revert to the original speed after PCIe failed link retraining
Sorry past few days have been struggling to buy some time to look at these. Every
time I go into the store and ask for more time they try to give me phone cards.
Its an improvement to restore the "capable" link speed & in this case I think we're
also enabling a user to have over-ridden it if they were to write the register
by hand. Its nice to give every potentially "new" device a chance at achieving
its full potential.
A little outside of the scope of this patch, but I was wondering if the logline
should be a warn level logline? I don't honestly know what a "normal" level is
for the pci system. Also, instead of saying "retraining ... at 2.5GT/s\n",
would it be more clear if it said "forcing downstream link to 2.5GT/s". In my mind
its more clear that an action has been taken which produces a potentially less
than unexpected speed.
I can test this patch on a couple of systems, but I need a week or so to
get it done...
Reviewed-by: Matthew Carlis <mattc@...estorage.com>
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