| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20240815071651.3645949-6-ye.zhang@rock-chips.com>
Date: Thu, 15 Aug 2024 15:16:51 +0800
From: Ye Zhang <ye.zhang@...k-chips.com>
To: linus.walleij@...aro.org,
brgl@...ev.pl,
heiko@...ech.de,
linux-gpio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Cc: linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
tao.huang@...k-chips.com,
finley.xiao@...k-chips.com,
tim.chen@...k-chips.com,
elaine.zhang@...k-chips.com,
Ye Zhang <ye.zhang@...k-chips.com>
Subject: [PATCH v1 5/5] rockchip: gpio: fix debounce config error
1. Prevent data from crossing boundaries
2. Support GPIO_TYPE_V2_2 debounce config
3. fix rockchip_gpio_set_config
Signed-off-by: Ye Zhang <ye.zhang@...k-chips.com>
---
drivers/gpio/gpio-rockchip.c | 42 ++++++++++++++++++++++--------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 03e949b0a344..186d8c750fce 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -84,7 +84,7 @@ static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
{
void __iomem *reg = bank->reg_base + offset;
- if (bank->gpio_type == GPIO_TYPE_V2)
+ if (bank->gpio_type >= GPIO_TYPE_V2)
gpio_writel_v2(value, reg);
else
writel(value, reg);
@@ -96,7 +96,7 @@ static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 value;
- if (bank->gpio_type == GPIO_TYPE_V2)
+ if (bank->gpio_type >= GPIO_TYPE_V2)
value = gpio_readl_v2(reg);
else
value = readl(reg);
@@ -111,7 +111,7 @@ static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 data;
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
if (value)
data = BIT(bit % 16) | BIT(bit % 16 + 16);
else
@@ -132,7 +132,7 @@ static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 data;
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
data = readl(bit >= 16 ? reg + 0x4 : reg);
data >>= bit % 16;
} else {
@@ -209,19 +209,25 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
unsigned int cur_div_reg;
u64 div;
- if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
- div_debounce_support = true;
+ div_debounce_support = (bank->gpio_type >= GPIO_TYPE_V2) && !IS_ERR(bank->db_clk);
+ if (debounce && div_debounce_support) {
freq = clk_get_rate(bank->db_clk);
if (!freq)
return -EINVAL;
- max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
+
+ div = (u64)(GENMASK(23, 0) + 1) * 1000000;
+ if (bank->gpio_type == GPIO_TYPE_V2)
+ max_debounce = DIV_ROUND_CLOSEST_ULL(div, freq);
+ else
+ max_debounce = DIV_ROUND_CLOSEST_ULL(div, 2 * freq);
if ((unsigned long)debounce > max_debounce)
return -EINVAL;
- div = debounce * freq;
- div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
- } else {
- div_debounce_support = false;
+ div = (u64)debounce * freq;
+ if (bank->gpio_type == GPIO_TYPE_V2)
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC) - 1;
+ else
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC / 2) - 1;
}
raw_spin_lock_irqsave(&bank->slock, flags);
@@ -284,10 +290,11 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
+ unsigned int debounce = pinconf_to_config_argument(config);
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
- rockchip_gpio_set_debounce(gc, offset, true);
+ rockchip_gpio_set_debounce(gc, offset, debounce);
/*
* Rockchip's gpio could only support up to one period
* of the debounce clock(pclk), which is far away from
@@ -416,7 +423,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
if (type == IRQ_TYPE_EDGE_BOTH) {
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 1,
bank->gpio_regs->int_bothedge);
goto out;
@@ -435,7 +442,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity |= mask;
}
} else {
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
bank->gpio_regs->int_bothedge);
} else {
@@ -543,7 +550,7 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
}
gc = irq_get_domain_generic_chip(bank->domain, 0);
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
gc->reg_writel = gpio_writel_v2;
gc->reg_readl = gpio_readl_v2;
}
@@ -632,10 +639,13 @@ static void rockchip_gpio_get_ver(struct rockchip_pin_bank *bank)
switch (id) {
case GPIO_TYPE_V2:
case GPIO_TYPE_V2_1:
- case GPIO_TYPE_V2_2:
bank->gpio_regs = &gpio_regs_v2;
bank->gpio_type = GPIO_TYPE_V2;
break;
+ case GPIO_TYPE_V2_2:
+ bank->gpio_regs = &gpio_regs_v2;
+ bank->gpio_type = GPIO_TYPE_V2_2;
+ break;
default:
bank->gpio_regs = &gpio_regs_v1;
bank->gpio_type = GPIO_TYPE_V1;
--
2.34.1
Powered by blists - more mailing lists