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Message-ID: <20240815-aspire-rocket-38a56ce389ae@spud>
Date: Thu, 15 Aug 2024 15:01:12 +0100
From: Conor Dooley <conor@...nel.org>
To: devicetree@...r.kernel.org
Cc: conor@...nel.org,
Conor Dooley <conor.dooley@...rochip.com>,
Lee Jones <lee@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-kernel@...r.kernel.org
Subject: [RFC PATCH 09/11] clk: microchip: mpfs: use regmap clock types
From: Conor Dooley <conor.dooley@...rochip.com>
Convert the PolarFire SoC clock driver to use regmap clock types as a
preparatory work for supporting the new binding for this device that
will only provide the second of the two register regions, and will
require the use of syscon regmap to access the "cfg" and "periph" clocks
currently supported by the driver.
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
drivers/clk/microchip/clk-mpfs.c | 81 ++++++++++++++++++++++----------
1 file changed, 56 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
index 28ec0da88cb3..e288c1729a23 100644
--- a/drivers/clk/microchip/clk-mpfs.c
+++ b/drivers/clk/microchip/clk-mpfs.c
@@ -6,10 +6,13 @@
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <dt-bindings/clock/microchip,mpfs-clock.h>
#include <soc/microchip/mpfs.h>
+#include "clk-regmap.h"
/* address offset of control registers */
#define REG_MSSPLL_REF_CR 0x08u
@@ -30,6 +33,14 @@
#define MSSPLL_POSTDIV_WIDTH 0x07u
#define MSSPLL_FIXED_DIV 4u
+static const struct regmap_config clk_mpfs_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+ .max_register = REG_SUBBLK_CLOCK_CR,
+};
+
/*
* This clock ID is defined here, rather than the binding headers, as it is an
* internal clock only, and therefore has no consumers in other peripheral
@@ -39,6 +50,7 @@
struct mpfs_clock_data {
struct device *dev;
+ struct regmap *regmap;
void __iomem *base;
void __iomem *msspll_base;
struct clk_hw_onecell_data hw_data;
@@ -68,14 +80,14 @@ struct mpfs_msspll_out_hw_clock {
#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)
struct mpfs_cfg_hw_clock {
- struct clk_divider cfg;
- struct clk_init_data init;
+ struct clk_regmap sigh;
+ struct clk_regmap_div_data cfg;
unsigned int id;
- u32 reg_offset;
};
struct mpfs_periph_hw_clock {
- struct clk_gate periph;
+ struct clk_regmap sigh;
+ struct clk_regmap_gate_data periph;
unsigned int id;
};
@@ -225,10 +237,9 @@ static int mpfs_clk_register_msspll_outs(struct device *dev,
.cfg.shift = _shift, \
.cfg.width = _width, \
.cfg.table = _table, \
- .reg_offset = _offset, \
+ .cfg.offset = _offset, \
.cfg.flags = _flags, \
- .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
- .cfg.lock = &mpfs_clk_lock, \
+ .sigh.hw.init = CLK_HW_INIT(_name, _parent, &clk_regmap_divider_ops, 0), \
}
#define CLK_CPU_OFFSET 0u
@@ -248,10 +259,10 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
.cfg.shift = 0,
.cfg.width = 12,
.cfg.table = mpfs_div_rtcref_table,
- .reg_offset = REG_RTC_CLOCK_CR,
+ .cfg.offset = REG_RTC_CLOCK_CR,
.cfg.flags = CLK_DIVIDER_ONE_BASED,
- .cfg.hw.init =
- CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
+ .sigh.hw.init =
+ CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_regmap_divider_ops, 0),
}
};
@@ -264,14 +275,16 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *
for (i = 0; i < num_clks; i++) {
struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
- cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
- ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
+ cfg_hw->sigh.map = data->regmap;
+ cfg_hw->sigh.data = &cfg_hw->cfg;
+
+ ret = devm_clk_hw_register(dev, &cfg_hw->sigh.hw);
if (ret)
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
cfg_hw->id);
id = cfg_hw->id;
- data->hw_data.hws[id] = &cfg_hw->cfg.hw;
+ data->hw_data.hws[id] = &cfg_hw->sigh.hw;
}
return 0;
@@ -283,13 +296,13 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *
#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
.id = _id, \
+ .periph.offset = REG_SUBBLK_CLOCK_CR, \
.periph.bit_idx = _shift, \
- .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
- _flags), \
- .periph.lock = &mpfs_clk_lock, \
+ .sigh.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_regmap_gate_ops, \
+ _flags), \
}
-#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
+#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].sigh.hw)
/*
* Critical clocks:
@@ -346,14 +359,15 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c
for (i = 0; i < num_clks; i++) {
struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
- periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
- ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
+ periph_hw->sigh.map = data->regmap;
+ periph_hw->sigh.data = &periph_hw->periph;
+ ret = devm_clk_hw_register(dev, &periph_hw->sigh.hw);
if (ret)
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
periph_hw->id);
id = periph_hws[i].id;
- data->hw_data.hws[id] = &periph_hw->periph.hw;
+ data->hw_data.hws[id] = &periph_hw->sigh.hw;
}
return 0;
@@ -374,6 +388,19 @@ static int mpfs_clk_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
+ clk_data->regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-mss-top-sysreg");
+ if (IS_ERR(clk_data->regmap)) {
+ clk_data->regmap = NULL;
+ goto old_format;
+ }
+
+ clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(clk_data->msspll_base))
+ return PTR_ERR(clk_data->msspll_base);
+
+ goto done;
+
+old_format:
clk_data->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(clk_data->base))
return PTR_ERR(clk_data->base);
@@ -382,6 +409,14 @@ static int mpfs_clk_probe(struct platform_device *pdev)
if (IS_ERR(clk_data->msspll_base))
return PTR_ERR(clk_data->msspll_base);
+ clk_data->regmap = devm_regmap_init_mmio(dev, clk_data->base, &clk_mpfs_regmap_config);
+ if (IS_ERR(clk_data->regmap))
+ return PTR_ERR(clk_data->regmap);
+
+ ret = mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
+ if (ret)
+ return ret;
+done:
clk_data->hw_data.num = num_clks;
clk_data->dev = dev;
dev_set_drvdata(dev, clk_data);
@@ -406,11 +441,7 @@ static int mpfs_clk_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
- if (ret)
- return ret;
-
- return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
}
static const struct of_device_id mpfs_clk_of_match_table[] = {
--
2.43.0
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