| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <10324095.IZOipudI63@diego>
Date: Thu, 15 Aug 2024 18:43:20 +0200
From: Heiko Stübner <heiko@...ech.de>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, Chris Morgan <macromorgan@...mail.com>,
Jonas Karlman <jonas@...boo.se>, Tim Lunn <tim@...thertop.org>,
Andy Yan <andyshrk@....com>, Muhammed Efe Cetin <efectn@...tonmail.com>,
Jagan Teki <jagan@...eble.ai>, Dragan Simic <dsimic@...jaro.org>,
Ondrej Jirman <megi@....cz>, Yao Zi <ziyao@...root.org>
Cc: Celeste Liu <CoelacanthusHex@...il.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
Yao Zi <ziyao@...root.org>
Subject: Re: [PATCH v3 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC
Hi,
Am Mittwoch, 14. August 2024, 17:50:13 CEST schrieb Yao Zi:
> This initial device tree describes CPU, interrupts and UART on the chip
> and is able to boot into basic kernel with only UART. Cache information
> is omitted for now as there is no precise documentation. Support for
> other features will be added later.
>
> Signed-off-by: Yao Zi <ziyao@...root.org>
not sure if you have seen Krzysztof's comment yesterday, that he found
the soc node getting documented in 2019 [0].
I guess that counts as a strong suggestion. Not sure how you're feeling
about that, but I guess we could move to that scheme for new socs.
So would you be willing to move the mmio-devices to a soc node?
(stuff with mmio addresses in the node name)
Thanks
Heiko
[0] https://lore.kernel.org/all/6320e4f3-e737-4787-8a72-7bd314ba883c@kernel.org/
> ---
> arch/arm64/boot/dts/rockchip/rk3528.dtsi | 182 +++++++++++++++++++++++
> 1 file changed, 182 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> new file mode 100644
> index 000000000000..816573c5fe9d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2024 Yao Zi <ziyao@...root.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "rockchip,rk3528";
> +
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + serial6 = &uart6;
> + serial7 = &uart7;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + xin24m: clock-xin24m {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "xin24m";
> + #clock-cells = <0>;
> + };
> +
> + gic: interrupt-controller@...01000 {
> + compatible = "arm,gic-400";
> + reg = <0x0 0xfed01000 0 0x1000>,
> + <0x0 0xfed02000 0 0x2000>,
> + <0x0 0xfed04000 0 0x2000>,
> + <0x0 0xfed06000 0 0x2000>;
> + interrupts = <GIC_PPI 9
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <3>;
> + };
> +
> + uart0: serial@...f0000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xff9f0000 0x0 0x100>;
> + clock-frequency = <24000000>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@...f8000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xff9f8000 0x0 0x100>;
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@...00000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xffa00000 0x0 0x100>;
> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@...08000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xffa08000 0x0 0x100>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@...10000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xffa10000 0x0 0x100>;
> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart5: serial@...18000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xffa18000 0x0 0x100>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart6: serial@...20000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xffa20000 0x0 0x100>;
> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart7: serial@...28000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xffa28000 0x0 0x100>;
> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +};
>
Powered by blists - more mailing lists