linux-kernel - [GIT PULL] RISC-V Fixes for 6.11-rc4

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Message-ID: <mhng-24597fb0-2ef5-4a27-ac81-cd0aa42fdd56@palmer-ri-x1c9>
Date: Fri, 16 Aug 2024 08:11:53 -0700 (PDT)
From: Palmer Dabbelt <palmer@...osinc.com>
To: Linus Torvalds <torvalds@...ux-foundation.org>
CC:         linux-riscv@...ts.infradead.org,        linux-kernel@...r.kernel.org
Subject: [GIT PULL] RISC-V Fixes for 6.11-rc4

The following changes since commit de9c2c66ad8e787abec7c9d7eff4f8c3cdd28aed:

  Linux 6.11-rc2 (2024-08-04 13:50:53 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.11-rc4

for you to fetch changes up to 32d5f7add080a936e28ab4142bfeea6b06999789:

  Merge patch series "RISC-V: hwprobe: Misaligned scalar perf fix and rename" (2024-08-15 13:12:21 -0700)

----------------------------------------------------------------
RISC-V Fixes for 6.11-rc4

* The text patching global icache flush has been reintroduced.
* A fix for the syscall entry code to correctly initialize a0, which
  manifests as a bug in strace.
* XIP kernels now map the entire kernel, which fixes boot under at least
  DEBUG_VIRTUAL=y.
* The acpi_early_node_map initializer now initializes all nodes.
* A fix for a OOB access in the Andes vendor extension probing code.
* A new key for scalar misaligned access performance in hwprobe, which
  correctly treat the values as an enum (as opposed to a bitmap).

----------------------------------------------------------------
That last patch set (for hwprobe) is sort of feature-smelling, but I think it's
sane to call it a fix -- it's kind of a grey area as to whether we even need a
new key, but we're playing it safe as hwprobe is such a compatibility-focused
interface.

----------------------------------------------------------------
Alexandre Ghiti (2):
      riscv: Re-introduce global icache flush in patch_text_XXX()
      riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array

Celeste Liu (1):
      riscv: entry: always initialize regs->a0 to -ENOSYS

Evan Green (2):
      RISC-V: hwprobe: Add MISALIGNED_PERF key
      RISC-V: hwprobe: Add SCALAR to misaligned perf defines

Haibo Xu (1):
      RISC-V: ACPI: NUMA: initialize all values of acpi_early_node_map to NUMA_NO_NODE

Nam Cao (1):
      riscv: change XIP's kernel_map.size to be size of the entire kernel

Palmer Dabbelt (1):
      Merge patch series "RISC-V: hwprobe: Misaligned scalar perf fix and rename"

 Documentation/arch/riscv/hwprobe.rst       | 36 ++++++++++++++++++------------
 arch/riscv/include/asm/hwprobe.h           |  2 +-
 arch/riscv/include/uapi/asm/hwprobe.h      |  6 +++++
 arch/riscv/kernel/acpi_numa.c              |  2 +-
 arch/riscv/kernel/patch.c                  |  4 ++++
 arch/riscv/kernel/sys_hwprobe.c            | 11 ++++-----
 arch/riscv/kernel/traps.c                  |  4 ++--
 arch/riscv/kernel/traps_misaligned.c       |  6 ++---
 arch/riscv/kernel/unaligned_access_speed.c | 12 +++++-----
 arch/riscv/kernel/vendor_extensions.c      |  2 +-
 arch/riscv/mm/init.c                       |  4 ++--
 11 files changed, 54 insertions(+), 35 deletions(-)