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Message-Id: <20240816-midas-audio-tab3-v2-4-48ee7f2293b3@gmail.com>
Date: Fri, 16 Aug 2024 09:51:01 +0200
From: Artur Weber <aweber.kernel@...il.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-sound@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
Artur Weber <aweber.kernel@...il.com>
Subject: [PATCH RESEND v2 4/6] ARM: dts: samsung: exynos4212-tab3: Add
MCLK2 clock to WM1811 codec config
In the schematics, the MCLK2 pin is shown as connected to CODEC_CLK32K,
which is derived from the same 32KHZ_PMIC clock as Bluetooth/WiFi and
GPS clocks. 32KHZ_PMIC is connected to the BTCLK pin, represented in
mainline as S2MPS11_CLK_BT.
Add the MCLK2 clock to the WM1811 codec clock property to properly
describe the hardware.
Signed-off-by: Artur Weber <aweber.kernel@...il.com>
---
arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
index bbafd4ece5f7..5106bb752b7d 100644
--- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
+++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
@@ -535,8 +535,9 @@ &i2c_4 {
wm1811: audio-codec@1a {
compatible = "wlf,wm1811";
reg = <0x1a>;
- clocks = <&pmu_system_controller 0>;
- clock-names = "MCLK1";
+ clocks = <&pmu_system_controller 0>,
+ <&s5m8767_osc S2MPS11_CLK_BT>;
+ clock-names = "MCLK1", "MCLK2";
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpx3>;
--
2.46.0
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