linux-kernel - Some feedbacks on RISC-V IOMMU driver

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Message-ID: <CAPYmKFsTcurrUiWqM8cFj+GgqfRiaLqPDGOTSE+RLyKJGSKE2g@mail.gmail.com>
Date: Mon, 19 Aug 2024 11:56:44 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: Tomasz Jeznach <tjeznach@...osinc.com>
Cc: joro@...tes.org, will@...nel.org, robin.murphy@....com, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Anup Patel <apatel@...tanamicro.com>, 
	sunilvl@...tanamicro.com, iommu@...ts.linux.dev, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux@...osinc.com, baolu.lu@...ux.intel.com, 
	Hangjing Li <lihangjing@...edance.com>, Yongji Xie <xieyongji@...edance.com>, 
	wangqian.rd@...edance.com
Subject: Some feedbacks on RISC-V IOMMU driver

Hi Tomasz,

Thanks for your brilliant job on RISC-V IOMMU driver. It helps us a
lot for what we are doing. Below is our feedback on the existing
implementation[1].

1) Some IOMMU HW may only support 32-bit granularity access on its
control registers (even when the register is 8 byte length). Maybe it
is better to provide a 32-bit access method for 8 byte length
registers like what opensbi does on ACLINT MTIME register.

2) In the IOMMU fault queue handling procedure, I wonder whether it is
better to clear the fqmf/fqof bit first, and then clear the ipsr.fip
bit. Otherwise the ipsr.fip can not be cleared and a redundant
interrupt will be signaled.

Best regards!
Xu Lu

[1] https://lore.kernel.org/all/cover.1718388908.git.tjeznach@rivosinc.com/