linux-kernel - Re: [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: add top-level constraints

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Message-ID: <172408768452.1698595.1459135684597826789.robh@kernel.org>
Date: Mon, 19 Aug 2024 11:14:45 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>,
	linux-renesas-soc@...r.kernel.org,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
	Marek Vasut <marek.vasut+renesas@...il.com>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Masami Hiramatsu <mhiramat@...nel.org>,
	Binghui Wang <wangbinghui@...ilicon.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
	linux-arm-kernel@...ts.infradead.org,
	Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
	Xiaowei Song <songxiaowei@...ilicon.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Magnus Damm <magnus.damm@...il.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	devicetree@...r.kernel.org
Subject: Re: [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: add
 top-level constraints


On Sun, 18 Aug 2024 19:28:43 +0200, Krzysztof Kozlowski wrote:
> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:".  Add missing top-level constraints
> for clock-names and reset-names.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
>  .../bindings/pci/socionext,uniphier-pcie-ep.yaml          | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>