linux-kernel - [PATCH v8 6/6] RISC-V: hwprobe: Document unaligned vector perf key

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Message-ID: <20240819212605.1837175-7-jesse@rivosinc.com>
Date: Mon, 19 Aug 2024 17:26:05 -0400
From: Jesse Taube <jesse@...osinc.com>
To: linux-riscv@...ts.infradead.org
Cc: Jonathan Corbet <corbet@....net>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Conor Dooley <conor@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Clément Léger <cleger@...osinc.com>,
	Evan Green <evan@...osinc.com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Jesse Taube <jesse@...osinc.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Xiao Wang <xiao.w.wang@...el.com>,
	Andy Chiu <andy.chiu@...ive.com>,
	Eric Biggers <ebiggers@...gle.com>,
	Greentime Hu <greentime.hu@...ive.com>,
	Björn Töpel <bjorn@...osinc.com>,
	Heiko Stuebner <heiko@...ech.de>,
	Costa Shulyupin <costa.shul@...hat.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Baoquan He <bhe@...hat.com>,
	Anup Patel <apatel@...tanamicro.com>,
	Zong Li <zong.li@...ive.com>,
	Sami Tolvanen <samitolvanen@...gle.com>,
	Ben Dooks <ben.dooks@...ethink.co.uk>,
	Alexandre Ghiti <alexghiti@...osinc.com>,
	"Gustavo A. R. Silva" <gustavoars@...nel.org>,
	Erick Archer <erick.archer@....com>,
	Joel Granados <j.granados@...sung.com>,
	linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org
Subject: [PATCH v8 6/6] RISC-V: hwprobe: Document unaligned vector perf key

Document key for reporting the speed of unaligned vector accesses.
The descriptions are the same as the scalar equivalent values.

Signed-off-by: Jesse Taube <jesse@...osinc.com>
Reviewed-by: Charlie Jenkins <charlie@...osinc.com>
---
V1 -> V2:
  - New patch
V2 -> V3:
 - Specify access width
V3 -> V4:
 - Clarify we're talking about byte accesses using vector registers
 - Spell out _VECTOR_ in macros
V4 -> V5:
 - No changes
V5 -> V6:
 - No changes
V6 -> V7:
 - No changes
V7 -> V8:
 - Rebase onto fixes
 - s/RISCV_HWPROBE_VECTOR_MISALIGNED/RISCV_HWPROBE_MISALIGNED_VECTOR/g
---
 Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 85b709257918..ea4e0b9c73e7 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -274,3 +274,19 @@ The following keys are defined:
   represent the highest userspace virtual address usable.
 
 * :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
+
+* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the
+     performance of misaligned vector accesses on the selected set of processors.
+
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned
+    vector accesses is unknown.
+
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector
+    registers are slower than the equivalent quantity of byte accesses via vector registers.
+    Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.
+
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector
+    registers are faster than the equivalent quantity of byte accesses via vector registers.
+
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are
+    not supported at all and will generate a misaligned address fault.
-- 
2.45.2