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Message-ID: <20240819090428.17349-1-eichest@gmail.com>
Date: Mon, 19 Aug 2024 11:03:16 +0200
From: Stefan Eichenberger <eichest@...il.com>
To: hongxing.zhu@....com,
l.stach@...gutronix.de,
lpieralisi@...nel.org,
kw@...ux.com,
robh@...nel.org,
bhelgaas@...gle.com,
shawnguo@...nel.org,
s.hauer@...gutronix.de,
kernel@...gutronix.de,
festevam@...il.com,
francesco.dolcini@...adex.com
Cc: linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
imx@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: [PATCH v1 0/3] PCI: imx6: reset link after suspend/resume
On the i.MX6Quad (not QuadPlus), the PCIe link does not work after a
suspend/resume cycle. Worse, the PCIe memory mapped I/O isn't accessible
at all, so the system freezes when a PCIe driver tries to access its I/O
space. The only way to get resume working again is to reset the PCIe
link, similar to what is done on devices that support suspend/resume.
Through trial and error, we found that something about the PCIe
reference clock does not work as expected after a resume. We could not
figure out if it is disabled (even though the registers still say it is
enabled), or if it is somehow unstable or has some hiccups. With the
workaround introduced in this patch series, we were able to fully resume
a Compex WLE900VX (ath10k) miniPCIe Wifi module and an Intel AX200 M.2
Wifi module. If there is a better way or other ideas on how to fix this
problem, please let us know. We are aware that resetting the link should
not be necessary, but we could not find a better solution. More
interestingly, even the SoCs that support suspend/resume according to
the i.MX erratas seem to reset the link on resume in
imx6_pcie_host_init, so we hope this might be a valid workaround.
Stefan Eichenberger (3):
PCI: imx6: Add a function to deassert the reset gpio
PCI: imx6: move the wait for clock stabilization to enable ref clk
PCI: imx6: reset link on resume
drivers/pci/controller/dwc/pci-imx6.c | 69 +++++++++++++++++++++++----
1 file changed, 59 insertions(+), 10 deletions(-)
--
2.43.0
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