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Message-ID: <16c70a037d912ec88eb9c082f35100c6@manjaro.org>
Date: Tue, 20 Aug 2024 16:28:07 +0200
From: Dragan Simic <dsimic@...jaro.org>
To: Chukun Pan <amadeus@....edu.cn>
Cc: Heiko Stuebner <heiko@...ech.de>, Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/1] arm64: dts: rockchip: disable display subsystem only
for Radxa E25
Hello Chukun,
On 2024-08-20 14:00, Chukun Pan wrote:
> The SoM board has reserved HDMI output, while the Radxa E25
> is not connected. So disable the display subsystem only for
> Radxa E25.
>
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>
Looking good to me, thanks for the patch. The carrier board is what's
responsible for exposing the actual HDMI port from the SoM.
Reviewed-by: Dragan Simic <dsimic@...jaro.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 4 ----
> arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 4 ++++
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
> index 45b03dcbbad4..19d309654bdb 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
> @@ -108,10 +108,6 @@ &cpu3 {
> cpu-supply = <&vdd_cpu>;
> };
>
> -&display_subsystem {
> - status = "disabled";
> -};
> -
> &gpu {
> mali-supply = <&vdd_gpu>;
> status = "okay";
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
> b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
> index 72ad74c38a2b..84a0789fad96 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
> @@ -103,6 +103,10 @@ &combphy1 {
> phy-supply = <&vcc3v3_pcie30x1>;
> };
>
> +&display_subsystem {
> + status = "disabled";
> +};
> +
> &pcie2x1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pcie20_reset_h>;
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