linux-kernel - RE: [PATCH v7 1/5] clk: samsung: exynosautov9: add dpum clock support

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Message-ID: <08f101daf2d7$afd0ad30$0f720790$@samsung.com>
Date: Tue, 20 Aug 2024 17:05:14 +0900
From: "sunyeal.hong" <sunyeal.hong@...sung.com>
To: "'Krzysztof Kozlowski'" <krzk@...nel.org>, "'Sylwester Nawrocki'"
	<s.nawrocki@...sung.com>, "'Chanwoo Choi'" <cw00.choi@...sung.com>, "'Alim
 Akhtar'" <alim.akhtar@...sung.com>, "'Michael Turquette'"
	<mturquette@...libre.com>, "'Stephen Boyd'" <sboyd@...nel.org>, "'Rob
 Herring'" <robh@...nel.org>, "'Conor Dooley'" <conor+dt@...nel.org>
Cc: <linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
	<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>, "'Kwanghoon Son'" <k.son@...sung.com>,
	"'Krzysztof	Kozlowski'" <krzysztof.kozlowski@...aro.org>
Subject: RE: [PATCH v7 1/5] clk: samsung: exynosautov9: add dpum clock
 support

Hello All,

Some incorrect patches were included. I will re-upload it to v8.

Best Regards,
sunyeal

> -----Original Message-----
> From: Sunyeal Hong <sunyeal.hong@...sung.com>
> Sent: Tuesday, August 20, 2024 4:45 PM
> To: Krzysztof Kozlowski <krzk@...nel.org>; Sylwester Nawrocki
> <s.nawrocki@...sung.com>; Chanwoo Choi <cw00.choi@...sung.com>; Alim
> Akhtar <alim.akhtar@...sung.com>; Michael Turquette
> <mturquette@...libre.com>; Stephen Boyd <sboyd@...nel.org>; Rob Herring
> <robh@...nel.org>; Conor Dooley <conor+dt@...nel.org>
> Cc: linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; Kwanghoon Son <k.son@...sung.com>; Krzysztof
> Kozlowski <krzysztof.kozlowski@...aro.org>
> Subject: [PATCH v7 1/5] clk: samsung: exynosautov9: add dpum clock support
> 
> From: Kwanghoon Son <k.son@...sung.com>
> 
> Add dpum clock for exynosautov9.
> 
> Signed-off-by: Kwanghoon Son <k.son@...sung.com>
> Link: https://lore.kernel.org/r/20240809-clk_dpum-v3-3-
> 359decc30fe2@...sung.com
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
>  drivers/clk/samsung/clk-exynosautov9.c | 83 ++++++++++++++++++++++++++
>  1 file changed, 83 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c
> b/drivers/clk/samsung/clk-exynosautov9.c
> index f04bacacab2c..5971e680e566 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -20,6 +20,7 @@
>  #define CLKS_NR_TOP			(GOUT_CLKCMU_PERIS_BUS + 1)
>  #define CLKS_NR_BUSMC			(CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
>  #define CLKS_NR_CORE			(CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
> +#define CLKS_NR_DPUM			(CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1)
>  #define CLKS_NR_FSYS0			(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK
> + 1)
>  #define CLKS_NR_FSYS1			(CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
>  #define CLKS_NR_FSYS2			(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO +
> 1)
> @@ -1076,6 +1077,85 @@ static const struct samsung_cmu_info core_cmu_info
> __initconst = {
>  	.clk_name		= "dout_clkcmu_core_bus",
>  };
> 
> +/* ---- CMU_DPUM
> +---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_DPUM (0x18c00000) */
> +#define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER				0x0600
> +#define CLK_CON_DIV_DIV_CLK_DPUM_BUSP					0x1800
> +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON
> 	0x202c
> +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA
> 	0x2030
> +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP
> 	0x2034
> +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1
> 	0x207c
> +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1
> 	0x2084
> +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1
> 	0x208c
> +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1
> 	0x2094
> +
> +static const unsigned long dpum_clk_regs[] __initconst = {
> +	PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER,
> +	CLK_CON_DIV_DIV_CLK_DPUM_BUSP,
> +	CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON,
> +	CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA,
> +	CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP,
> +	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1,
> +	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1,
> +	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1,
> +	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1,
> +};
> +
> +PNAME(mout_dpum_bus_user_p) = { "oscclk", "dout_clkcmu_dpum_bus" };
> +
> +static const struct samsung_mux_clock dpum_mux_clks[] __initconst = {
> +	MUX(CLK_MOUT_DPUM_BUS_USER, "mout_dpum_bus_user",
> +	    mout_dpum_bus_user_p, PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, 4,
> 1), };
> +
> +static const struct samsung_div_clock dpum_div_clks[] __initconst = {
> +	DIV(CLK_DOUT_DPUM_BUSP, "dout_dpum_busp", "mout_dpum_bus_user",
> +	    CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 0, 3), };
> +
> +static const struct samsung_gate_clock dpum_gate_clks[] __initconst = {
> +	GATE(CLK_GOUT_DPUM_ACLK_DECON, "gout_dpum_decon_aclk",
> +	     "mout_dpum_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, 21,
> +	     0, 0),
> +	GATE(CLK_GOUT_DPUM_ACLK_DMA, "gout_dpum_dma_aclk",
> "mout_dpum_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, 21,
> +	     0, 0),
> +	GATE(CLK_GOUT_DPUM_ACLK_DPP, "gout_dpum_dpp_aclk",
> "mout_dpum_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, 21,
> +	     0, 0),
> +	GATE(CLK_GOUT_DPUM_SYSMMU_D0_CLK, "gout_dpum_sysmmu_d0_clk",
> +	     "mout_dpum_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1,
> 21,
> +	     0, 0),
> +	GATE(CLK_GOUT_DPUM_SYSMMU_D1_CLK, "gout_dpum_sysmmu_d1_clk",
> +	     "mout_dpum_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1,
> 21,
> +	     0, 0),
> +	GATE(CLK_GOUT_DPUM_SYSMMU_D2_CLK, "gout_dpum_sysmmu_d2_clk",
> +	     "mout_dpum_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1,
> 21,
> +	     0, 0),
> +	GATE(CLK_GOUT_DPUM_SYSMMU_D3_CLK, "gout_dpum_sysmmu_d3_clk",
> +	     "mout_dpum_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1,
> 21,
> +	     0, 0),
> +};
> +
> +static const struct samsung_cmu_info dpum_cmu_info __initconst = {
> +	.mux_clks		= dpum_mux_clks,
> +	.nr_mux_clks		= ARRAY_SIZE(dpum_mux_clks),
> +	.div_clks		= dpum_div_clks,
> +	.nr_div_clks		= ARRAY_SIZE(dpum_div_clks),
> +	.gate_clks		= dpum_gate_clks,
> +	.nr_gate_clks		= ARRAY_SIZE(dpum_gate_clks),
> +	.nr_clk_ids		= CLKS_NR_DPUM,
> +	.clk_regs		= dpum_clk_regs,
> +	.nr_clk_regs		= ARRAY_SIZE(dpum_clk_regs),
> +	.clk_name		= "bus",
> +};
> +
>  /* ---- CMU_FSYS0 -------------------------------------------------------
> --- */
> 
>  /* Register Offset definitions for CMU_FSYS2 (0x17700000) */ @@ -2085,6
> +2165,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] =
> {
>  	}, {
>  		.compatible = "samsung,exynosautov9-cmu-core",
>  		.data = &core_cmu_info,
> +	}, {
> +		.compatible = "samsung,exynosautov9-cmu-dpum",
> +		.data = &dpum_cmu_info,
>  	}, {
>  		.compatible = "samsung,exynosautov9-cmu-fsys0",
>  		.data = &fsys0_cmu_info,
> --
> 2.45.2
>