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Message-Id: <20240821055136.6858-1-ada@thorsis.com>
Date: Wed, 21 Aug 2024 07:51:36 +0200
From: Alexander Dahl <ada@...rsis.com>
To: linux-clk@...r.kernel.org
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Claudiu Beznea <claudiu.beznea@...on.dev>,
Codrin Ciubotariu <codrin.ciubotariu@...rochip.com>,
Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@...rochip.com>,
Nicolas Ferre <nicolas.ferre@...rochip.com>,
Tudor Ambarus <tudor.ambarus@...aro.org>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH v2] ARM: dts: microchip: sam9x60: Fix rtc/rtt clocks
The RTC and RTT peripherals use the "timing domain slow clock (TD_SLCK),
sourced from the 32.768 kHz crystal oscillator.
(The previously used Monitoring domain slow clock (MD_SLCK) is sourced
from an internal RC oscillator which is most probably not precise enough
for real time clock purposes.)
Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
Fixes: 5f6b33f46346 ("ARM: dts: sam9x60: add rtt")
Signed-off-by: Alexander Dahl <ada@...rsis.com>
---
Notes:
Picked the wrong patch in the first try. This v2 one has a slightly
adapted commit message and more context below.
This obviously requires a 32.768 kHz crystal oscillator to be present,
but the sam9x60.dtsi does contain that, and the clock-controllers
reference that, so I assume it's always present.
/sys/kernel/debug/clk/clk_summary content excerpt before:
slow_rc_osc 1 1 0 32768 93750000 0 50000 Y deviceless no_connection_id
md_slck 4 4 0 32768 0 0 50000 Y fffffea8.rtc no_connection_id
fffffe20.rtc no_connection_id
fffffe10.poweroff no_connection_id
fffffe00.reset-controller no_connection_id
timer@...08000 slow_clk
deviceless no_connection_id
…
slow_xtal 0 0 0 32768 0 0 50000 Y deviceless no_connection_id
slow_osc 0 0 0 32768 0 0 50000 Y deviceless no_connection_id
td_slck 0 0 0 32768 0 0 50000 Y deviceless no_connection_id
And after:
slow_rc_osc 1 1 0 32768 93750000 0 50000 Y deviceless no_connection_id
md_slck 2 2 0 32768 0 0 50000 Y fffffe10.poweroff no_connection_id
fffffe00.reset-controller no_connection_id
timer@...08000 slow_clk
deviceless no_connection_id
…
slow_xtal 1 1 0 32768 0 0 50000 Y deviceless no_connection_id
slow_osc 1 1 0 32768 0 0 50000 Y deviceless no_connection_id
td_slck 2 2 0 32768 0 0 50000 Y fffffea8.rtc no_connection_id
fffffe20.rtc no_connection_id
deviceless no_connection_id
arch/arm/boot/dts/microchip/sam9x60.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index 291540e5d81e..d077afd5024d 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -1312,7 +1312,7 @@ rtt: rtc@...ffe20 {
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xfffffe20 0x20>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k 1>;
};
pit: timer@...ffe40 {
@@ -1338,7 +1338,7 @@ rtc: rtc@...ffea8 {
compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
reg = <0xfffffea8 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k 1>;
};
watchdog: watchdog@...fff80 {
base-commit: 47ac09b91befbb6a235ab620c32af719f8208399
--
2.39.2
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