lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <13b66efe-ed51-4e62-a0ea-f2f97b4144e8@lunn.ch>
Date: Thu, 22 Aug 2024 21:53:58 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Imran Shaik <quic_imrashai@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Richard Cochran <richardcochran@...il.com>,
	Ajit Pandey <quic_ajipan@...cinc.com>,
	Taniya Das <quic_tdas@...cinc.com>,
	Jagadeesh Kona <quic_jkona@...cinc.com>,
	Satya Priya Kakitapalli <quic_skakitap@...cinc.com>,
	linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org
Subject: Re: [PATCH 2/2] clk: qcom: Add support for Global Clock Controller
 on QCS8300

On Wed, Aug 21, 2024 at 01:54:57PM +0530, Imran Shaik wrote:
> 
> 
> On 8/20/2024 7:36 PM, Andrew Lunn wrote:
> > > +static int gcc_qcs8300_probe(struct platform_device *pdev)
> > > +{
> > > +	struct regmap *regmap;
> > > +	int ret;
> > > +
> > > +	regmap = qcom_cc_map(pdev, &gcc_qcs8300_desc);
> > > +	if (IS_ERR(regmap))
> > > +		return PTR_ERR(regmap);
> > > +
> > > +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> > > +				       ARRAY_SIZE(gcc_dfs_clocks));
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	/* Keep some clocks always enabled */
> > > +	qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */
> > > +	qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */
> > 
> > It would be good to document why. Why does the camera driver not
> > enable the clock when it loads?
> > 
> > > +	qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */
> > > +	qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */
> > > +	qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */
> > > +	qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
> > > +	qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
> > 
> > Why cannot the display driver enable the clock when it loads?
> > 
> 
> These clocks require for DISPCC and CAMCC drivers for register access, hence
> kept enabled at GCC driver probe. The same approach is followed for all the
> targets.

No, the DISPCC and CAMCC driver should get and enable these clocks
before accessing the hardware. They should be turned off until then,
and maybe they will never be used if it is a headless box without a
camera.

	Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ