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Message-ID: <20240822221938.2192109-2-kim.phillips@amd.com>
Date: Thu, 22 Aug 2024 17:19:37 -0500
From: Kim Phillips <kim.phillips@....com>
To: <kvm@...r.kernel.org>, <linux-coco@...ts.linux.dev>,
<linux-kernel@...r.kernel.org>, <x86@...nel.org>
CC: Tom Lendacky <thomas.lendacky@....com>, Michael Roth
<michael.roth@....com>, Ashish Kalra <ashish.kalra@....com>, "Nikunj A .
Dadhania" <nikunj@....com>, Borislav Petkov <bp@...en8.de>, Dave Hansen
<dave.hansen@...ux.intel.com>, Sean Christopherson <seanjc@...gle.com>,
"Paolo Bonzini" <pbonzini@...hat.com>, Ingo Molnar <mingo@...hat.com>, "H.
Peter Anvin" <hpa@...or.com>, Thomas Gleixner <tglx@...utronix.de>, Kim
Phillips <kim.phillips@....com>
Subject: [PATCH v2 1/2] x86/cpufeatures: Add "Allowed SEV Features" Feature
Add CPU feature detection for "Allowed SEV Features" to allow the
Hypervisor to enforce that SEV-ES and SEV-SNP guest VMs cannot
enable features (via SEV_FEATURES) that the Hypervisor does not
support or wish to be enabled.
Signed-off-by: Kishon Vijay Abraham I <kvijayab@....com>
Signed-off-by: Kim Phillips <kim.phillips@....com>
---
v2: no changes
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index dd4682857c12..0c73da91a041 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -447,6 +447,7 @@
#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */
#define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */
#define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */
+#define X86_FEATURE_ALLOWED_SEV_FEATURES (19*32+27) /* AMD Allowed SEV Features */
#define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */
/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
--
2.34.1
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