linux-kernel - Re: [PATCH v3 4/4] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB

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Message-ID: <CALMp9eTcKk-zKTJzD+wkA_5RE=7rs+qcvhF6tgOBoYfw5GetyQ@mail.gmail.com>
Date: Fri, 23 Aug 2024 15:00:03 -0700
From: Jim Mattson <jmattson@...gle.com>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Tom Lendacky <thomas.lendacky@....com>, Thomas Gleixner <tglx@...utronix.de>, 
	Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>, 
	Dave Hansen <dave.hansen@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>, 
	Paolo Bonzini <pbonzini@...hat.com>, Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>, 
	Josh Poimboeuf <jpoimboe@...nel.org>, Sandipan Das <sandipan.das@....com>, 
	Kai Huang <kai.huang@...el.com>, x86@...nel.org, linux-kernel@...r.kernel.org, 
	kvm@...r.kernel.org, Venkatesh Srinivas <venkateshs@...omium.org>
Subject: Re: [PATCH v3 4/4] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB

On Fri, Aug 23, 2024 at 1:51 PM Sean Christopherson <seanjc@...gle.com> wrote:
>
> On Fri, Aug 23, 2024, Tom Lendacky wrote:
> > On 8/23/24 13:53, Jim Mattson wrote:
> > > From Intel's documention [1], "CPUID.(EAX=07H,ECX=0):EDX[26]
> > > enumerates support for indirect branch restricted speculation (IBRS)
> > > and the indirect branch predictor barrier (IBPB)." Further, from [2],
> > > "Software that executed before the IBPB command cannot control the
> > > predicted targets of indirect branches (4) executed after the command
> > > on the same logical processor," where footnote 4 reads, "Note that
> > > indirect branches include near call indirect, near jump indirect and
> > > near return instructions. Because it includes near returns, it follows
> > > that **RSB entries created before an IBPB command cannot control the
> > > predicted targets of returns executed after the command on the same
> > > logical processor.**" [emphasis mine]
> > >
> > > On the other hand, AMD's IBPB "may not prevent return branch
> > > predictions from being specified by pre-IBPB branch targets" [3].
> > >
> > > However, some AMD processors have an "enhanced IBPB" [terminology
> > > mine] which does clear the return address predictor. This feature is
> > > enumerated by CPUID.80000008:EDX.IBPB_RET[bit 30] [4].
> > >
> > > Adjust the cross-vendor features enumerated by KVM_GET_SUPPORTED_CPUID
> > > accordingly.
> > >
> > > [1] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html
> > > [2] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/speculative-execution-side-channel-mitigations.html#Footnotes
> > > [3] https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1040.html
> > > [4] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf
> > >
> > > Fixes: 0c54914d0c52 ("KVM: x86: use Intel speculation bugs and features as derived in generic x86 code")
> > > Suggested-by: Venkatesh Srinivas <venkateshs@...omium.org>
> > > Signed-off-by: Jim Mattson <jmattson@...gle.com>
> > > ---
> > >  arch/x86/kvm/cpuid.c | 6 +++++-
> > >  1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> > > index ec7b2ca3b4d3..c8d7d928ffc7 100644
> > > --- a/arch/x86/kvm/cpuid.c
> > > +++ b/arch/x86/kvm/cpuid.c
> > > @@ -690,7 +690,9 @@ void kvm_set_cpu_caps(void)
> > >     kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
> > >     kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
> > >
> > > -   if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
> > > +   if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) &&
> > > +       boot_cpu_has(X86_FEATURE_AMD_IBPB) &&
> > > +       boot_cpu_has(X86_FEATURE_AMD_IBRS))
> > >             kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
> > >     if (boot_cpu_has(X86_FEATURE_STIBP))
> > >             kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
> > > @@ -759,6 +761,8 @@ void kvm_set_cpu_caps(void)
> > >      * arch/x86/kernel/cpu/bugs.c is kind enough to
> > >      * record that in cpufeatures so use them.
> > >      */
> > > +   if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
> > > +           kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET);
> >
> > If SPEC_CTRL is set, then IBPB is set, so you can't have AMD_IBPB_RET
> > without AMD_IBPB, but it just looks odd seeing them set with separate
> > checks with no relationship dependency for AMD_IBPB_RET on AMD_IBPB.
> > That's just me, though, not worth a v4 unless others feel the same.
>
> You thinking something like this (at the end, after the dust settles)?
>
>         if (WARN_ON_ONCE(kvm_cpu_cap_has(X86_FEATURE_AMD_IBPB_RET) &&
>                          !kvm_cpu_cap_has(X86_FEATURE_AMD_IBPB)))
>                 kvm_cpu_cap_clear(X86_FEATURE_AMD_IBPB_RET);
> >

Ugh. No.

I think it would be better to replace the subsequent vendor-neutral
tests with something like:

    if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) {
        kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
        kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET);
        kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
    }

Again, my real preference is to leave the cross-vendor enumeration to
userspace, but I guess that ship has sailed.

> > Thanks,
> > Tom
> >
> > >     if (boot_cpu_has(X86_FEATURE_IBPB))
> > >             kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
> > >     if (boot_cpu_has(X86_FEATURE_IBRS))