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Message-Id: <20240823034314.62305-9-ye.zhang@rock-chips.com>
Date: Fri, 23 Aug 2024 11:43:11 +0800
From: Ye Zhang <ye.zhang@...k-chips.com>
To: linus.walleij@...aro.org,
brgl@...ev.pl,
heiko@...ech.de,
linux-gpio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Cc: linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
mika.westerberg@...ux.intel.com,
andriy.shevchenko@...ux.intel.com,
tao.huang@...k-chips.com,
finley.xiao@...k-chips.com,
tim.chen@...k-chips.com,
elaine.zhang@...k-chips.com,
Ye Zhang <ye.zhang@...k-chips.com>
Subject: [PATCH v2] gpio: rockchip: support new version gpio
The next version gpio controller on SoCs like rk3576 which support four
OS operation and four interrupts
Signed-off-by: Ye Zhang <ye.zhang@...k-chips.com>
---
drivers/gpio/gpio-rockchip.c | 40 ++++++++++++++++++++++++------------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 25ddf6a82c09..5289c94d5c60 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -29,6 +29,7 @@
#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
#define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
+#define GPIO_TYPE_V2_2 (0x010219C8) /* GPIO Version ID 0x010219C8 */
static const struct rockchip_gpio_regs gpio_regs_v1 = {
.port_dr = 0x00,
@@ -78,7 +79,7 @@ static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
{
void __iomem *reg = bank->reg_base + offset;
- if (bank->gpio_type == GPIO_TYPE_V2)
+ if (bank->gpio_type >= GPIO_TYPE_V2)
gpio_writel_v2(value, reg);
else
writel(value, reg);
@@ -90,7 +91,7 @@ static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 value;
- if (bank->gpio_type == GPIO_TYPE_V2)
+ if (bank->gpio_type >= GPIO_TYPE_V2)
value = gpio_readl_v2(reg);
else
value = readl(reg);
@@ -105,7 +106,7 @@ static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 data;
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
if (value)
data = BIT(bit % 16) | BIT(bit % 16 + 16);
else
@@ -126,7 +127,7 @@ static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 data;
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
data = readl(bit >= 16 ? reg + 0x4 : reg);
data >>= bit % 16;
} else {
@@ -204,18 +205,24 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
unsigned int cur_div_reg;
u64 div;
- div_debounce_support = (bank->gpio_type == GPIO_TYPE_V2) && !IS_ERR(bank->db_clk);
+ div_debounce_support = (bank->gpio_type >= GPIO_TYPE_V2) && !IS_ERR(bank->db_clk);
if (debounce && div_debounce_support) {
freq = clk_get_rate(bank->db_clk);
if (!freq)
return -EINVAL;
div = (u64)(GENMASK(23, 0) + 1) * 1000000;
- max_debounce = DIV_ROUND_CLOSEST_ULL(div, freq);
+ if (bank->gpio_type == GPIO_TYPE_V2)
+ max_debounce = DIV_ROUND_CLOSEST_ULL(div, freq);
+ else
+ max_debounce = DIV_ROUND_CLOSEST_ULL(div, 2 * freq);
if (debounce > max_debounce)
return -EINVAL;
div = (u64)debounce * freq;
- div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC) - 1;
+ if (bank->gpio_type == GPIO_TYPE_V2)
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC) - 1;
+ else
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC / 2) - 1;
}
raw_spin_lock_irqsave(&bank->slock, flags);
@@ -401,7 +408,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
if (type == IRQ_TYPE_EDGE_BOTH) {
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 1,
bank->gpio_regs->int_bothedge);
goto out;
@@ -420,7 +427,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity |= mask;
}
} else {
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
bank->gpio_regs->int_bothedge);
} else {
@@ -526,7 +533,7 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
}
gc = irq_get_domain_generic_chip(bank->domain, 0);
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
gc->reg_writel = gpio_writel_v2;
gc->reg_readl = gpio_readl_v2;
}
@@ -648,13 +655,20 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
id = readl(bank->reg_base + gpio_regs_v2.version_id);
- /* If not gpio v2, that is default to v1. */
- if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
+ switch (id) {
+ case GPIO_TYPE_V2:
+ case GPIO_TYPE_V2_1:
bank->gpio_regs = &gpio_regs_v2;
bank->gpio_type = GPIO_TYPE_V2;
- } else {
+ break;
+ case GPIO_TYPE_V2_2:
+ bank->gpio_regs = &gpio_regs_v2;
+ bank->gpio_type = GPIO_TYPE_V2_2;
+ break;
+ default:
bank->gpio_regs = &gpio_regs_v1;
bank->gpio_type = GPIO_TYPE_V1;
+ pr_info("Note: Use default GPIO_TYPE_V1!\n");
}
return 0;
--
2.34.1
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