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Message-ID: <34e8083e-1439-442d-a979-03ac5b65ae38@linux.intel.com>
Date: Fri, 23 Aug 2024 13:13:43 +0300
From: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
To: Shyam Sundar S K <Shyam-sundar.S-k@....com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>
Cc: Guruvendra Punugupati <Guruvendra.Punugupati@....com>,
Krishnamoorthi M <krishnamoorthi.m@....com>, linux-i3c@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 6/6] i3c: mipi-i3c-hci: Add a quirk to set Response
buffer threshold
On 8/21/24 4:35 PM, Shyam Sundar S K wrote:
> The current driver sets the response buffer threshold value to 1
> (N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD
> I3C controller only generates interrupts when the response buffer
> threshold value is set to 0 (1 DWORD).
>
> Therefore, a quirk is added to set the response buffer threshold value
> to 0.
>
> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@....com>
> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@....com>
> Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@....com>
> Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@....com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@....com>
> ---
> drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++++-
> drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++
> drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 11 +++++++++++
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
Reviewed-by: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
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