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Message-ID: <e06a3bd9-6378-2d4b-b06d-cc2d58776eca@gentwo.org>
Date: Fri, 23 Aug 2024 18:57:43 -0700 (PDT)
From: "Christoph Lameter (Ampere)" <cl@...two.org>
To: Yunhui Cui <cuiyunhui@...edance.com>
cc: punit.agrawal@...edance.com, paul.walmsley@...ive.com, palmer@...belt.com, 
    aou@...s.berkeley.edu, dennis@...nel.org, tj@...nel.org, 
    samitolvanen@...gle.com, guoren@...nel.org, debug@...osinc.com, 
    charlie@...osinc.com, cleger@...osinc.com, puranjay@...nel.org, 
    antonb@...storrent.com, namcaov@...il.com, andy.chiu@...ive.com, 
    ajones@...tanamicro.com, samuel.holland@...ive.com, haxel@....de, 
    yang.zhang@...intek.com, conor.dooley@...rochip.com, evan@...osinc.com, 
    yang.lee@...ux.alibaba.com, tglx@...utronix.de, haibo1.xu@...el.com, 
    linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
    linux-mm@...ck.org
Subject: Re: [PATCH RFC] riscv: use gp to save percpu offset

On Sat, 24 Aug 2024, Yunhui Cui wrote:

> Compared to directly fetching the per-CPU offset from memory (or cache),
> using the global pointer (gp) to store the per-CPU offset can save one
> memory access.

Yes! That is a step in the right direction.

Is there something like gp relative addressing so that we can do loads
and stores relative to gp as well?

Are there atomics that can do read modify write relative to GP? That would
get  you to comparable per cpu efficiency to x86. x86 can do relative
addressing and RMV in one instruction which allows one to drop the preempt
enable/disable since one instruction cannot be interrupted.

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