diff --git a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
index e6047fbbea76..2a338d6b8bbf 100644
--- a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
+++ b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
@@ -191,50 +191,44 @@ static int write_eff_lat_ctrl(struct uncore_data *data, unsigned int val, enum u
 	case UNCORE_INDEX_EFF_LAT_CTRL_LOW_THRESHOLD:
 		if (val > FIELD_MAX(UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK))
 			return -EINVAL;
+
+		control = readq(cluster_info->cluster_base + UNCORE_CONTROL_INDEX);
+		control &= ~UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK;
+		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK, val);
 		break;
 
 	case UNCORE_INDEX_EFF_LAT_CTRL_HIGH_THRESHOLD:
 		if (val > FIELD_MAX(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK))
 			return -EINVAL;
+
+		control = readq(cluster_info->cluster_base + UNCORE_CONTROL_INDEX);
+		control &= ~UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK;
+		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK, val);
 		break;
 
 	case UNCORE_INDEX_EFF_LAT_CTRL_HIGH_THRESHOLD_ENABLE:
 		if (val > 1)
 			return -EINVAL;
+
+		control = readq(cluster_info->cluster_base + UNCORE_CONTROL_INDEX);
+		control &= ~UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_ENABLE;
+		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_ENABLE, val);
 		break;
 
 	case UNCORE_INDEX_EFF_LAT_CTRL_FREQ:
 		val /= UNCORE_FREQ_KHZ_MULTIPLIER;
 		if (val > FIELD_MAX(UNCORE_EFF_LAT_CTRL_RATIO_MASK))
 			return -EINVAL;
+
+		control = readq(cluster_info->cluster_base + UNCORE_CONTROL_INDEX);
+		control &= ~UNCORE_EFF_LAT_CTRL_RATIO_MASK;
+		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_RATIO_MASK, val);
 		break;
 
 	default:
 		return -EOPNOTSUPP;
 	}
 
-	control = readq(cluster_info->cluster_base + UNCORE_CONTROL_INDEX);
-
-	if (index == UNCORE_INDEX_EFF_LAT_CTRL_LOW_THRESHOLD) {
-		control &= ~UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK;
-		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK, val);
-	}
-
-	if (index == UNCORE_INDEX_EFF_LAT_CTRL_HIGH_THRESHOLD) {
-		control &= ~UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK;
-		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK, val);
-	}
-
-	if (index == UNCORE_INDEX_EFF_LAT_CTRL_HIGH_THRESHOLD_ENABLE) {
-		control &= ~UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_ENABLE;
-		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_ENABLE, val);
-	}
-
-	if (index == UNCORE_INDEX_EFF_LAT_CTRL_FREQ) {
-		control &= ~UNCORE_EFF_LAT_CTRL_RATIO_MASK;
-		control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_RATIO_MASK, val);
-	}
-
 	writeq(control, cluster_info->cluster_base + UNCORE_CONTROL_INDEX);
 
 	return 0;