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Message-ID: <CAJZ5v0imJcU4cwDuZKEvGf93fZm4ea4s2Ocp3Cnfb3+nBQ0-Gg@mail.gmail.com>
Date: Mon, 26 Aug 2024 18:15:18 +0200
From: "Rafael J. Wysocki" <rafael@...nel.org>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Sunil V L <sunilvl@...tanamicro.com>, "Rafael J . Wysocki" <rafael@...nel.org>,
Will Deacon <will@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Len Brown <lenb@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>, Anup Patel <anup@...infault.org>,
Samuel Holland <samuel.holland@...ive.com>, Robert Moore <robert.moore@...el.com>,
Conor Dooley <conor.dooley@...rochip.com>, Haibo Xu <haibo1.xu@...el.com>,
Andrew Jones <ajones@...tanamicro.com>, Atish Kumar Patra <atishp@...osinc.com>,
Drew Fustini <dfustini@...storrent.com>, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-riscv@...ts.infradead.org,
linux-acpi@...r.kernel.org, acpica-devel@...ts.linux.dev
Subject: Re: [PATCH v8 00/17] RISC-V: ACPI: Add external interrupt controller support
On Mon, Aug 26, 2024 at 5:25 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>
> On Mon, Aug 12 2024 at 06:37, Sunil V. L. wrote:
> > On Mon, Aug 12, 2024 at 06:29:12AM +0530, Sunil V L wrote:
> >> This series adds support for the below ECR approved by ASWG.
> >> 1) MADT - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing
> >>
> >> The series primarily enables irqchip drivers for RISC-V ACPI based
> >> platforms.
> >
> > This series has spent quite a bit of time now on the list. As you are
> > aware, few clarifications like _PIC codes are also done now. There is
> > no major change after you had agreed for the design. So, can this be
> > considered for the next release please?
>
> Rafael, if you want to take it through the ACPI tree, then for the
> irqchip parts please add:
>
> Acked-by: Thomas Gleixner <tglx@...utronix.de>
Yes, I'm going ro do this.
Thank you!
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