linux-kernel - Re: [PATCH v3 1/4] x86/cpufeatures: Clarify semantics of X86_FEATURE

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Message-ID: <20240826203308.litigvo6zomwapws@desk>
Date: Mon, 26 Aug 2024 13:33:08 -0700
From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To: Jim Mattson <jmattson@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
	Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	Sean Christopherson <seanjc@...gle.com>,
	Paolo Bonzini <pbonzini@...hat.com>,
	Josh Poimboeuf <jpoimboe@...nel.org>,
	Sandipan Das <sandipan.das@....com>,
	Kai Huang <kai.huang@...el.com>, x86@...nel.org,
	linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Subject: Re: [PATCH v3 1/4] x86/cpufeatures: Clarify semantics of
 X86_FEATURE_IBPB

On Fri, Aug 23, 2024 at 11:53:10AM -0700, Jim Mattson wrote:
> Since this synthetic feature bit is set on AMD CPUs that don't flush
> the RSB on an IBPB, indicate as much in the comment, to avoid
> potential confusion with the Intel IBPB semantics.
> 
> Signed-off-by: Jim Mattson <jmattson@...gle.com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index dd4682857c12..cabd6b58e8ec 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -215,7 +215,7 @@
>  #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* Disable Speculative Store Bypass. */
>  #define X86_FEATURE_LS_CFG_SSBD		( 7*32+24)  /* AMD SSBD implementation via LS_CFG MSR */
>  #define X86_FEATURE_IBRS		( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */
> -#define X86_FEATURE_IBPB		( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */
> +#define X86_FEATURE_IBPB		( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without RSB flush */

I don't think the comment is accurate for Intel. Maybe you meant to modify
X86_FEATURE_AMD_IBPB?