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Message-ID: <CAF6AEGs23d5OqKst+ik-kMMXPCS_0=-a8ndskv3j4NduOVR1Vw@mail.gmail.com>
Date: Mon, 26 Aug 2024 14:07:44 -0700
From: Rob Clark <robdclark@...il.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: Sean Paul <sean@...rly.run>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>, Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio <konrad.dybcio@...aro.org> wrote:
>
> This was apparently almost never set on a6xx.. move the existing values
> and fill out the remaining ones within the catalog.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++----
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> 3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 1ea535960f32..deee0b686962 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -448,7 +448,6 @@ static const struct adreno_reglist a690_hwcg[] = {
> {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> - {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> {}
> @@ -636,6 +635,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a612_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00080000,
> },
> /*
> @@ -668,6 +668,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00180000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -691,6 +692,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .init = a6xx_gpu_init,
> .a6xx = &(const struct a6xx_info) {
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00180000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -714,6 +716,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00018000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -737,6 +740,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00018000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -760,6 +764,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00018000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -788,6 +793,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a630_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00180000,
> },
> }, {
> @@ -806,6 +812,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a640_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00180000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -829,6 +836,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a650_hwcg,
> .protect = &a650_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00300200,
> },
> .address_space_size = SZ_16G,
> @@ -855,6 +863,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a660_hwcg,
> .protect = &a660_protect,
> + .gmu_cgc_mode = 0x00020000,
> .prim_fifo_threshold = 0x00300200,
> },
> .address_space_size = SZ_16G,
> @@ -874,6 +883,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a660_hwcg,
> .protect = &a660_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00200200,
> },
> .address_space_size = SZ_16G,
> @@ -899,6 +909,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a640_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00200200,
> },
> }, {
> @@ -917,6 +928,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a690_hwcg,
> .protect = &a690_protect,
> + .gmu_cgc_mode = 0x00020200,
> .prim_fifo_threshold = 0x00800200,
> },
> .address_space_size = SZ_16G,
> @@ -1178,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a702_hwcg,
> .protect = &a650_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x0000c000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -1202,6 +1215,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a730_hwcg,
> .protect = &a730_protect,
> + .gmu_cgc_mode = 0x00020000,
> },
> .address_space_size = SZ_16G,
> }, {
> @@ -1221,6 +1235,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .hwcg = a740_hwcg,
> .protect = &a730_protect,
> .gmu_chipid = 0x7020100,
> + .gmu_cgc_mode = 0x00020202,
> },
> .address_space_size = SZ_16G,
> }, {
> @@ -1239,6 +1254,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .hwcg = a740_hwcg,
> .protect = &a730_protect,
> .gmu_chipid = 0x7050001,
> + .gmu_cgc_mode = 0x00020202,
> },
> .address_space_size = SZ_256G,
> }, {
> @@ -1257,6 +1273,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .protect = &a730_protect,
> .gmu_chipid = 0x7090100,
> + .gmu_cgc_mode = 0x00020202,
> },
> .address_space_size = SZ_16G,
> }
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index aaeb1161f90d..871452daa189 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
> const struct adreno_reglist *reg;
> unsigned int i;
> - u32 val, clock_cntl_on, cgc_mode;
> + u32 val, clock_cntl_on;
>
> if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
> return;
> @@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> clock_cntl_on = 0x8aa8aa82;
>
> if (adreno_is_a7xx(adreno_gpu)) {
> - cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
> -
This does appear to change the gmu_cgc_mode in nearly all cases.. was
this intended?
BR,
-R
> gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
> - state ? cgc_mode : 0);
> + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
> gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
> state ? 0x10111 : 0);
> gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index bc37bd8c7f65..0fb7febf70e7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -22,6 +22,7 @@ struct a6xx_info {
> const struct adreno_reglist *hwcg;
> const struct adreno_protect *protect;
> u32 gmu_chipid;
> + u32 gmu_cgc_mode;
> u32 prim_fifo_threshold;
> };
>
>
> --
> 2.45.2
>
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