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Message-ID: <20240826071641.2691374-3-manojvishy@google.com>
Date: Mon, 26 Aug 2024 07:16:39 +0000
From: Manoj Vishwanathan <manojvishy@...gle.com>
To: Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>, 
	Joerg Roedel <joro@...tes.org>, Alex Williamson <alex.williamson@...hat.com>, 
	linux-arm-kernel@...ts.infradead.org
Cc: kvm@...r.kernel.org, iommu@...ts.linux.dev, linux-kernel@...r.kernel.org, 
	David Dillow <dillow@...gle.com>, Manoj Vishwanathan <manojvishy@...gle.com>
Subject: [PATCH v1 2/4] iommu/io-pgtable-arm: Force outer cache for page-level
 MAIR via user flag

This change introduces a user-accessible flag that allows controlling
the system-level outer cache behavior for mapped buffers.

By setting this flag, the page-level MAIR attribute will be forced to
use the outer cache, potentially improving performance for frequently
accessed data.

Signed-off-by: Manoj Vishwanathan <manojvishy@...gle.com>
---
 drivers/iommu/io-pgtable-arm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index f5d9fd1f45bf..31dd6203db96 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -471,6 +471,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
 		else if (prot & IOMMU_CACHE)
 			pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
 				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
+		else if (prot & IOMMU_SYS_CACHE)
+			pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
+				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
 	}
 
 	/*
-- 
2.46.0.295.g3b9ea8a38a-goog


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