linux-kernel - Re: [PATCH v3 1/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC

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Message-ID: <CAMuHMdWC0sgF48Thdg95zyPn04XJv1H+ZScXZrUfzcp8v738ag@mail.gmail.com>
Date: Mon, 26 Aug 2024 12:38:15 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3 1/8] arm64: dts: renesas: Add initial SoC DTSI for
 RZ/V2H(P) SoC

Hi Prabhakar,

On Wed, Aug 21, 2024 at 10:56 AM Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are
> the list of blocks added:
> - EXT CLKs
> - 4X CA55
> - SCIF
> - PFC
> - CPG
> - SYS
> - GIC
> - ARMv8 Timer
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v2->v3
> - Updated GIC node to match with the coding-style of DTS

Thanks for the update!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -0,0 +1,165 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/V2H(P) SoC
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       compatible = "renesas,r9a09g057";
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       audio_extal_clk: audio-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       rtxin_clk: rtxin-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       qextal_clk: qextal-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };

Please use alphabetical sort order (by nodename).

> +       soc: soc {
> +               compatible = "simple-bus";
> +               interrupt-parent = <&gic>;
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               pinctrl: pinctrl@...10000 {
> +                       compatible = "renesas,r9a09g057-pinctrl";
> +                       reg = <0 0x10410000 0 0x10000>;
> +                       clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       gpio-ranges = <&pinctrl 0 0 96>;
> +                       #interrupt-cells = <2>;
> +                       interrupt-controller;
> +                       power-domains = <&cpg>;
> +                       resets = <&cpg 165>, <&cpg 166>;

Please use hexadecimal reset numbers, cfr. the description in the DT
bindings. E.g. IOTOP_0_RESETN = CPG_RST_10 bit 5 => 0xa5.

This comment applies to all resets in this series.

> +               };

> +               scif: serial@...01400 {
> +                       compatible = "renesas,scif-r9a09g057";
> +                       reg = <0 0x11c01400 0 0x400>;
> +                       interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "eri", "rxi", "txi", "bri", "dri",
> +                                         "tei", "tei-dri", "rxi-edge", "txi-edge";
> +                       clocks = <&cpg CPG_MOD 143>;

Please use hexadecimal module clock numbers, cfr. the description in
the DT bindings. E.g. CGC_SCIF_0_clk_pck = CPG_CLKON_8 bit 15 => 0x8f.

This comment applies to all module clocks in this series.

> +                       clock-names = "fck";
> +                       power-domains = <&cpg>;
> +                       resets = <&cpg 149>;
> +                       status = "disabled";
> +               };

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds