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Message-ID: <7be4da2d.a8a2.1918e5ba74b.Coremail.andyshrk@163.com>
Date: Mon, 26 Aug 2024 19:04:16 +0800 (CST)
From: "Andy Yan" <andyshrk@....com>
To: "Detlev Casanova" <detlev.casanova@...labora.com>
Cc: linux-kernel@...r.kernel.org, "Michael Turquette" <mturquette@...libre.com>,
"Stephen Boyd" <sboyd@...nel.org>, "Rob Herring" <robh@...nel.org>,
"Krzysztof Kozlowski" <krzk+dt@...nel.org>,
"Conor Dooley" <conor+dt@...nel.org>,
"Heiko Stuebner" <heiko@...ech.de>,
"Philipp Zabel" <p.zabel@...gutronix.de>,
"Elaine Zhang" <zhangqing@...k-chips.com>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, kernel@...labora.com,
"Sugar Zhang" <sugar.zhang@...k-chips.com>
Subject: Re:[PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576
Hi Deltev，
Thanks for your work。
At 2024-08-23 03:49:32, "Detlev Casanova" <detlev.casanova@...labora.com> wrote:
>Add clock and reset ID defines for rk3576.
>
>Compared to the downstream bindings written by Elaine, this uses
>continous gapless IDs starting at 0. Thus all numbers are
>different between downstream and upstream, but names are kept
>exactly the same.
>
>Also add documentation for the rk3576 CRU core.
>
>Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
>Signed-off-by: Sugar Zhang <sugar.zhang@...k-chips.com>
>Signed-off-by: Detlev Casanova <detlev.casanova@...labora.com>
>---
> .../bindings/clock/rockchip,rk3576-cru.yaml | 56 ++
> .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++++++++++++++
> .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++++++++++++++
> 3 files changed, 1212 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml
> create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h
> create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h
>
>diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml
>new file mode 100644
>index 000000000000..9c9b36049c71
>--- /dev/null
>+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml
>@@ -0,0 +1,56 @@
>+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Rockchip rk3576 Family Clock and Reset Control Module
>+
>+maintainers:
>+ - Elaine Zhang <zhangqing@...k-chips.com>
>+ - Heiko Stuebner <heiko@...ech.de>
>+ - Detlev Casanova <detlev.casanova@...labora.com>
>+
>+description:
>+ The RK3576 clock controller generates the clock and also implements a reset
>+ controller for SoC peripherals. For example it provides SCLK_UART2 and
>+ PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
>+ module.
>+
>+properties:
>+ compatible:
>+ const: rockchip,rk3576-cru
>+
>+ reg:
>+ maxItems: 1
>+
>+ "#clock-cells":
>+ const: 1
>+
>+ "#reset-cells":
>+ const: 1
>+
>+ clocks:
>+ maxItems: 2
>+
>+ clock-names:
>+ items:
>+ - const: xin24m
>+ - const: xin32k
>+
>+required:
>+ - compatible
>+ - reg
>+ - "#clock-cells"
>+ - "#reset-cells"
>+
>+additionalProperties: false
>+
>+examples:
>+ - |
>+ clock-controller@...00000 {
>+ compatible = "rockchip,rk3576-cru";
>+ reg = <0xfd7c0000 0x5c000>;
>+ #clock-cells = <1>;
>+ #reset-cells = <1>;
>+ };
>diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h
>new file mode 100644
>index 000000000000..ee3718452b77
>--- /dev/null
>+++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h
>@@ -0,0 +1,592 @@
>+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>+/*
>+* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
>+* Copyright (c) 2024 Collabora Ltd.
>+*
>+* Author: Elaine Zhang <zhangqing@...k-chips.com>
>+* Author: Detlev Casanova <detlev.casanova@...labora.com>
>+*/
>+
>+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
>+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
>+
>+/* cru-clocks indices */
>+
>+/* cru plls */
>+#define PLL_BPLL 0
>+#define PLL_LPLL 1
>+#define PLL_VPLL 2
>+#define PLL_AUPLL 3
>+#define PLL_CPLL 4
>+#define PLL_GPLL 5
>+#define PLL_PPLL 6
>+#define ARMCLK_L 7
>+#define ARMCLK_B 8
>+
>+/* cru clocks */
>+#define CLK_CPLL_DIV20 9
>+#define CLK_CPLL_DIV10 10
>+#define CLK_GPLL_DIV8 11
>+#define CLK_GPLL_DIV6 12
.........
>+#define SRST_OTGPHY_1 449
>+#define SRST_HDPTX_INIT 450
>+#define SRST_HDPTX_CMN 451
>+#define SRST_HDPTX_LANE 452
>+#define SRST_HDMITXHPD 453
Compared to RK3588, this should be SRST_HDMITXHDP . I think this is a typo in TRM。
>+
>+#define SRST_MPHY_INIT 454
>+#define SRST_P_MPHY_GRF 455
>+#define SRST_P_VCCIO7_IOC 456
>+
>+#define SRST_H_PMU1_BIU 457
>+#define SRST_P_PMU1_NIU 458
>+#define SRST_H_PMU_CM0_BIU 459
>+#define SRST_PMU_CM0_CORE 460
>+#define SRST_PMU_CM0_JTAG 461
>+
>+#define SRST_P_CRU_PMU1 462
>+#define SRST_P_PMU1_GRF 463
>+#define SRST_P_PMU1_IOC 464
>+#define SRST_P_PMU1WDT 465
>+#define SRST_T_PMU1WDT 466
>+#define SRST_P_PMUTIMER 467
>+#define SRST_PMUTIMER0 468
>+#define SRST_PMUTIMER1 469
>+#define SRST_P_PMU1PWM 470
>+#define SRST_PMU1PWM 471
>+
>+#define SRST_P_I2C0 472
>+#define SRST_I2C0 473
>+#define SRST_S_UART1 474
>+#define SRST_P_UART1 475
>+#define SRST_PDM0 476
>+#define SRST_H_PDM0 477
>+
>+#define SRST_M_PDM0 478
>+#define SRST_H_VAD 479
>+
>+#define SRST_P_PMU0GRF 480
>+#define SRST_P_PMU0IOC 481
>+#define SRST_P_GPIO0 482
>+#define SRST_DB_GPIO0 483
>+
>+#endif
>--
>2.46.0
>
>
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