linux-kernel - Re: [PATCH 3/6] dt-bindings: pinctrl: Add fsl,ls1012a-pinctrl yaml file

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Message-ID: <db12d221-d3b1-4df5-91e4-d31fb0acdb8b@kernel.org>
Date: Tue, 27 Aug 2024 19:28:41 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: David Leonard <David.Leonard@...i.com>
Cc: linux-arm-kernel@...ts.infradead.org, Dong Aisheng
 <aisheng.dong@....com>, Fabio Estevam <festevam@...il.com>,
 Shawn Guo <shawnguo@...nel.org>, Jacky Bai <ping.bai@....com>,
 Pengutronix Kernel Team <kernel@...gutronix.de>,
 Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, linux-gpio@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/6] dt-bindings: pinctrl: Add fsl,ls1012a-pinctrl yaml
 file

On 27/08/2024 18:51, David Leonard wrote:
>>> +properties:
>>> +  compatible:
>>> +    const: fsl,ls1012a-pinctrl
>>> +
>>> +  reg:
>>> +    description: Specifies the base address of the PMUXCR0 register.
>>> +    maxItems: 2
>>
>> Instead list and describe the items.
> 
> Changed to
> 
>     reg:
>       items:
>         - description: Physical base address of the PMUXCR0 register.
>         - description: Size of the PMUXCR0 register (4).
> 
> Is this what you meant?

Almost, second reg is not a size. You claim there are two IO address
spaces. Each address space contains base address and size. Look at other
bindings how they do it.



> 
>>> +
>>> +  big-endian:
>>> +    description: If present, the PMUXCR0 register is implemented in big-endian.
>>
>> Why is this here? Either it is or it is not?
> 
> You're right. Changed to
> 
>     big-endian: true
> 
> (This also lead to some code simplification)

OK, but I still wonder why is it here. Without it the hardware will work
in little-endian?

> 


Best regards,
Krzysztof