linux-kernel - Re: [PATCH] arm64: dts: ti: k3-j784s4-main: align watchdog clocks

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Message-ID: <hqifchzwvzyexlcq6vfhlnrp3sixkgk23vau6o46k6einn5vee@gj5a53ee2gsi>
Date: Tue, 27 Aug 2024 16:56:39 -0500
From: Andrew Halaney <ahalaney@...hat.com>
To: Eric Chanudet <echanude@...hat.com>
Cc: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>, 
	Tero Kristo <kristo@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: ti: k3-j784s4-main: align watchdog clocks

On Mon, Aug 05, 2024 at 01:42:51PM GMT, Eric Chanudet wrote:
> assigned-clock sets DEV_RTIx_RTI_CLK(id:0) whereas clocks sets
> DEV_RTIx_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT(id:1)[1]. This does not
> look right, the timers in the driver assume a max frequency of 32kHz for
> the heartbeat (HFOSC0 is 19.2MHz on j784s4-evm).
> 
> With this change, WDIOC_GETTIMELEFT return coherent time left
> (DEFAULT_HEARTBEAT=60, reports 60s upon opening the cdev).
> 
> [1] http://downloads.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html#clocks-for-rti0-device
> 
> Fixes: caae599de8c6 ("arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances")
> Suggested-by: Andrew Halaney <ahalaney@...hat.com>
> Signed-off-by: Eric Chanudet <echanude@...hat.com>

Tested-by: Andrew Halaney <ahalaney@...hat.com>

As mentioned throughout the other thread, you need the r5 u-boot build to
configure the ESMs and the PMIC properly to get the board to actually
reset (not in upstream u-boot at the moment).

This patch fixes the watchdog itself though, prior timeleft was
bogus etc but with this patch it starts at 60 sec (default) and reboots
when we hit 0.

Still an open question about the ESM(s) and their relationship with the
PMIC, but that's an entirely independent subject to this fix.

Thanks,
Andrew