linux-kernel - Re: [PATCH v2 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT

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Message-ID: <CA+V-a8siwvOxB-RF1BtQ9kj2=aJAVP+-Nx9YkSNj+o67zTc=JA@mail.gmail.com>
Date: Tue, 27 Aug 2024 14:05:38 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset
 entries for GTM/RIIC/SDHI/WDT

Hi Geert,

Thank you for the review.

On Mon, Aug 26, 2024 at 2:37 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Aug 22, 2024 at 1:16 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > v1->v2
> > - Updated DDIV_PACK macro to accommodate width
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/rzv2h-cpg.h
> > +++ b/drivers/clk/renesas/rzv2h-cpg.h
> > @@ -8,6 +8,13 @@
> >  #ifndef __RENESAS_RZV2H_CPG_H__
> >  #define __RENESAS_RZV2H_CPG_H__
> >
> > +#define CPG_CDDIV0             (0x400)
> > +
> > +#define DDIV_PACK(offset, bitpos, mon, size) \
> > +               (((mon) << 19) | ((offset) << 8) | ((bitpos) << 4) | (size))
>
> I think the DDIV_PACK() macro (using C bitfields?) belongs in the
> previous patch.
>
Agreed, I'll move the updated macro (below) to patch 1/2

#define DDIV_PACK(_offset, _shift, _width, _monbit) \
    ((struct ddiv){ \
        .offset = _offset, \
        .shift = _shift, \
        .width = _width, \
        .monbit = _monbit \
    })


Cheers,
Prabhakar