Message-Id: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org>
Date: Wed, 28 Aug 2024 21:16:10 +0530
From: Manivannan Sadhasivam via B4 Relay <devnull+manivannan.sadhasivam.linaro.org@...nel.org>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>, 
 Krzysztof Wilczyński <kw@...ux.com>, 
 Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Kishon Vijay Abraham I <kishon@...nel.org>, 
 Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org, 
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
 Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, 
 Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [PATCH v4 00/12] PCI: qcom: Enumerate endpoints based on Link up
 event in 'global_irq' interrupt

Hi,

This series adds support to enumerate the PCIe endpoint devices using the Qcom
specific 'Link up' event in 'global' IRQ. Historically, Qcom PCIe RC controllers
lacked standard hotplug support. So when an endpoint is attached to the SoC,
users have to rescan the bus manually to enumerate the device. But this can be
avoided by rescanning the bus upon receiving 'Link up' event.

Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt
to the host CPUs. The device driver can use this interrupt to identify events
such as PCIe link specific events, safety events etc...

One such event is the PCIe Link up event generated when an endpoint is detected
on the bus and the Link is 'up'. This event can be used to enumerate the
endpoint devices.

So add support for capturing the PCIe Link up event using the 'global' interrupt
in the driver. Once the Link up event is received, the bus underneath the host
bridge is scanned to enumerate PCIe endpoint devices.

This series also has some cleanups to the Qcom PCIe EP controller driver for
interrupt handling.

NOTE: During v2 review, there was a discussion about removing the devices when
'Link Down' event is received. But this needs some more investigation, so I'm
planning to add it later.

Testing
=======

This series is tested on Qcom SM8450 based development board that has 2 SoCs
connected over PCIe.

Merging Strategy
================

I'm expecting the binding and PCI driver changes to go through PCI tree and DTS
patches through Qcom tree.

- Mani

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
---
Changes in v4:
- Fixed the indendation issue reported by Kbot
- Merged the bindings patch adding global IRQ into one as suggested by Rob
- Collected review tag
- Link to v3: https://lore.kernel.org/r/20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org

Changes in v3:
- Removed the usage of 'simulating hotplug' and just used 'Link up' as we are
  not fully emulating the hotplug support
- Fixed the build issue wtih CONFIG_PCI_DOMAINS_GENERIC
- Moved the 'global' IRQ entry to last in the binding and also mentioned the ABI
  break and its necessity in patch description.
- Collected tags
- Rebased on top of v6.11-rc1
- Link to v2: https://lore.kernel.org/r/20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org

Changes in v2:
- Added CONFIG_PCI_DOMAINS_GENERIC guard for domain_nr
- Switched to dev_WARN_ONCE() for unhandled interrupts
- Squashed the 'linux,pci-domain' bindings patches into one
- Link to v1: https://lore.kernel.org/r/20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org

---
Manivannan Sadhasivam (12):
      PCI: qcom-ep: Drop the redundant masking of global IRQ events
      PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
      dt-bindings: PCI: pci-ep: Update Maintainers
      dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property
      PCI: endpoint: Assign PCI domain number for endpoint controllers
      PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
      ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node
      ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node
      arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes
      dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt
      PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
      arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node

 Documentation/devicetree/bindings/pci/pci-ep.yaml  | 14 +++++-
 .../devicetree/bindings/pci/qcom,pcie-common.yaml  |  4 +-
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml      |  1 +
 .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml  | 10 ++--
 arch/arm/boot/dts/qcom/qcom-sdx55.dtsi             |  1 +
 arch/arm/boot/dts/qcom/qcom-sdx65.dtsi             |  1 +
 arch/arm64/boot/dts/qcom/sa8775p.dtsi              |  2 +
 arch/arm64/boot/dts/qcom/sm8450.dtsi               | 12 +++--
 drivers/pci/controller/dwc/pcie-qcom-ep.c          | 21 +++++++--
 drivers/pci/controller/dwc/pcie-qcom.c             | 55 +++++++++++++++++++++-
 drivers/pci/endpoint/pci-epc-core.c                | 14 ++++++
 include/linux/pci-epc.h                            |  2 +
 12 files changed, 120 insertions(+), 17 deletions(-)
---
base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b
change-id: 20240715-pci-qcom-hotplug-bcde1c13d91f

Best regards,
-- 
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>

Powered by blists - more mailing lists