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Message-ID: <1c7fb593-9080-43fc-bcb4-3028acb2abbb@quicinc.com>
Date: Wed, 28 Aug 2024 13:33:56 -0700
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Bjorn Andersson
<andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
"Stephen
Boyd" <sboyd@...nel.org>, Jonathan Marek <jonathan@...ek.ca>,
Robert Foss
<rfoss@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Rob Clark
<robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Marijn Suijten
<marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, "Daniel
Vetter" <daniel@...ll.ch>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
"Georgi
Djakov" <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
"Krzysztof
Kozlowski" <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
"Mike
Tipton" <quic_mdtipton@...cinc.com>,
Catalin Marinas
<catalin.marinas@....com>,
Will Deacon <will@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-pm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 03/11] drm/msm/dsi: correct programming sequence for
SM8350 / SM8450
On 8/3/2024 10:40 PM, Dmitry Baryshkov wrote:
> According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
> different boundaries for pll_clock_inverters programming. Follow the
> vendor code and use correct values.
>
> Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 3b59137ca674..031446c87dae 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -135,7 +135,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
> config->pll_clock_inverters = 0x00;
> else
> config->pll_clock_inverters = 0x40;
> - } else {
> + } else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> if (pll_freq <= 1000000000ULL)
> config->pll_clock_inverters = 0xa0;
> else if (pll_freq <= 2500000000ULL)
> @@ -144,6 +144,16 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
> config->pll_clock_inverters = 0x00;
> else
> config->pll_clock_inverters = 0x40;
> + } else {
> + /* 4.2, 4.3 */
> + if (pll_freq <= 1000000000ULL)
> + config->pll_clock_inverters = 0xa0;
> + else if (pll_freq <= 2500000000ULL)
> + config->pll_clock_inverters = 0x20;
> + else if (pll_freq <= 3500000000ULL)
> + config->pll_clock_inverters = 0x00;
> + else
> + config->pll_clock_inverters = 0x40;
> }
Sorry for the delay, my request for the docs was first rejected for some
reason :)
Now I finally got access and this matches the docs
Reviewed-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
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