linux-kernel - RE: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT

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Message-ID:
 <TY3PR01MB113460F2ABA56C89E8E9CF09D86952@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Wed, 28 Aug 2024 10:10:10 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
CC: Geert Uytterhoeven <geert+renesas@...der.be>, Michael Turquette
	<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Fabrizio
 Castro <fabrizio.castro.jz@...esas.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset
 entries for GTM/RIIC/SDHI/WDT



> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@...il.com>
> Sent: Wednesday, August 28, 2024 11:00 AM
> Subject: Re: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for
> GTM/RIIC/SDHI/WDT
> 
> Hi Biju,
> 
> On Wed, Aug 28, 2024 at 10:53 AM Biju Das <biju.das.jz@...renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@...il.com>
> > > Sent: Wednesday, August 28, 2024 10:38 AM
> > > Subject: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for
> GTM/RIIC/SDHI/WDT
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > ---
> > > v2->v3
> > > - Moved DDIV_PACK() macro to patch #1
> > >
> > > v1->v2
> > > - Updated DDIV_PACK macro to accommodate width
> > > ---
> > >  drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
> > >  drivers/clk/renesas/rzv2h-cpg.h     |  4 ++
> > >  2 files changed, 88 insertions(+)
> > >
> > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > > index 9722b810e027..3ee32db5c0af 100644
> > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > > @@ -25,16 +25,31 @@ enum clk_ids {
> > >
> > >       /* PLL Clocks */
> > >       CLK_PLLCM33,
> > > +     CLK_PLLCLN,
> > >       CLK_PLLDTY,
> > >       CLK_PLLCA55,
> > >
> > >       /* Internal Core Clocks */
> > >       CLK_PLLCM33_DIV16,
> > > +     CLK_PLLCLN_DIV2,
> > > +     CLK_PLLCLN_DIV8,
> > > +     CLK_PLLCLN_DIV16,
> > > +     CLK_PLLDTY_ACPU,
> > > +     CLK_PLLDTY_ACPU_DIV4,
> > >
> > >       /* Module Clocks */
> > >       MOD_CLK_BASE,
> > >  };
> > >
> > > +static const struct clk_div_table dtable_2_64[] = {
> > > +     {0, 2},
> > > +     {1, 4},
> > > +     {2, 8},
> > > +     {3, 16},
> > > +     {4, 64},
> > > +     {0, 0},
> >
> > Is it ok to have {0, 2} first entry and {0, 0} last entry on the same table?
> >
> You mean is it prohibited to add (I haven't seen issues)?

2 different divider values{2, 0) for the value 0 in the table. You maybe correct.

Cheers,
Biju