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Message-ID: <20240829091713.736217-6-Shyam-sundar.S-k@amd.com>
Date: Thu, 29 Aug 2024 14:47:12 +0530
From: Shyam Sundar S K <Shyam-sundar.S-k@....com>
To: Alexandre Belloni <alexandre.belloni@...tlin.com>, Jarkko Nikula
<jarkko.nikula@...ux.intel.com>
CC: Guruvendra Punugupati <Guruvendra.Punugupati@....com>, Krishnamoorthi M
<krishnamoorthi.m@....com>, <linux-i3c@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, Shyam Sundar S K <Shyam-sundar.S-k@....com>
Subject: [PATCH v6 5/6] i3c: mipi-i3c-hci: Add a quirk to set timing parameters
The AMD HCI controller is currently unstable at 12.5 MHz. To address this,
a quirk is added to configure the clock rate to 9 MHz as a workaround,
with proportional adjustments to the Open-Drain (OD) and Push-Pull (PP)
values.
Reviewed-by: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@....com>
Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@....com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@....com>
---
drivers/i3c/master/mipi-i3c-hci/Makefile | 3 +-
drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++-
drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++
drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 33 ++++++++++++++++++++
4 files changed, 42 insertions(+), 2 deletions(-)
create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile
index a658e7b8262c..1f8cd5c48fde 100644
--- a/drivers/i3c/master/mipi-i3c-hci/Makefile
+++ b/drivers/i3c/master/mipi-i3c-hci/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci.o
mipi-i3c-hci-y := core.o ext_caps.o pio.o dma.o \
cmd_v1.o cmd_v2.o \
- dat_v1.o dct_v1.o
+ dat_v1.o dct_v1.o \
+ hci_quirks.o
diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index c03e86690073..f9ce0ee2cfd5 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -785,6 +785,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
return ret;
}
+ /* Configure OD and PP timings for AMD platforms */
+ if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
+ amd_set_od_pp_timing(hci);
+
return 0;
}
@@ -838,7 +842,7 @@ static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
static const struct acpi_device_id i3c_hci_acpi_match[] = {
- { "AMDI5017", HCI_QUIRK_PIO_MODE },
+ { "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING },
{}
};
MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match);
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index 76658789b018..361e1366fe38 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -141,11 +141,13 @@ struct i3c_hci_dev_data {
/* list of quirks */
#define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */
#define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */
+#define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */
/* global functions */
void mipi_i3c_hci_resume(struct i3c_hci *hci);
void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
+void amd_set_od_pp_timing(struct i3c_hci *hci);
#endif
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
new file mode 100644
index 000000000000..e8ea4d101f66
--- /dev/null
+++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * I3C HCI Quirks
+ *
+ * Copyright 2024 Advanced Micro Devices, Inc.
+ *
+ * Authors: Shyam Sundar S K <Shyam-sundar.S-k@....com>
+ * Guruvendra Punugupati <Guruvendra.Punugupati@....com>
+ */
+
+#include <linux/i3c/master.h>
+#include "hci.h"
+
+/* Timing registers */
+#define HCI_SCL_I3C_OD_TIMING 0x214
+#define HCI_SCL_I3C_PP_TIMING 0x218
+#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230
+
+/* Timing values to configure 9MHz frequency */
+#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf
+#define AMD_SCL_I3C_PP_TIMING 0x00160016
+
+void amd_set_od_pp_timing(struct i3c_hci *hci)
+{
+ u32 data;
+
+ reg_write(HCI_SCL_I3C_OD_TIMING, AMD_SCL_I3C_OD_TIMING);
+ reg_write(HCI_SCL_I3C_PP_TIMING, AMD_SCL_I3C_PP_TIMING);
+ data = reg_read(HCI_SDA_HOLD_SWITCH_DLY_TIMING);
+ /* Configure maximum TX hold time */
+ data |= W0_MASK(18, 16);
+ reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
+}
--
2.25.1
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