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Message-ID: <CAA8EJpoN-rWiKj37-9QGRVOJSXd0sk7kKbmO8VJEHQoyse6s3w@mail.gmail.com>
Date: Thu, 29 Aug 2024 14:56:46 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Jun Nie <jun.nie@...aro.org>
Cc: Rob Clark <robdclark@...il.com>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 20/21] drm/msm/dpu: support quad pipe in general operations
On Thu, 29 Aug 2024 at 13:21, Jun Nie <jun.nie@...aro.org> wrote:
>
> Support quad pipe in general operations with unified method.
>
> Signed-off-by: Jun Nie <jun.nie@...aro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 87 +++++++++++++++++--------------
> 1 file changed, 47 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index c38c1bedd40fb..c3ea97b4ce439 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -619,6 +619,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
> struct msm_drm_private *priv = plane->dev->dev_private;
> struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
> + int i;
>
> DPU_DEBUG_PLANE(pdpu, "\n");
>
> @@ -632,12 +633,11 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
> return;
>
> /* update sspp */
> - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect,
> - fill_color, fmt);
> -
> - if (pstate->r_pipe.sspp)
> - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect,
> - fill_color, fmt);
> + for (i = 0; i < PIPES_PER_STAGE; i++)
> + if (pstate->pipe[i].sspp)
> + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i],
> + &pstate->pipe_cfg[i].dst_rect,
> + fill_color, fmt);
> }
>
> static int dpu_plane_prepare_fb(struct drm_plane *plane,
> @@ -1279,8 +1279,11 @@ void dpu_plane_flush(struct drm_plane *plane)
> /* force 100% alpha */
> _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
> else {
> - dpu_plane_flush_csc(pdpu, &pstate->pipe);
> - dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
> + int i;
> +
> + for (i = 0; i < PIPES_PER_STAGE; i++)
> + if (pstate->pipe_cfg[i].visible)
> + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]);
> }
>
> /* flag h/w flush complete */
> @@ -1380,20 +1383,17 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> struct drm_plane_state *state = plane->state;
> struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> - struct dpu_sw_pipe *pipe = &pstate->pipe;
> - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
> struct drm_crtc *crtc = state->crtc;
> struct drm_framebuffer *fb = state->fb;
> bool is_rt_pipe;
> const struct msm_format *fmt =
> msm_framebuffer_format(fb);
> - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
> - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
> + struct dpu_sw_pipe_cfg *pipe_cfg;
> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
> struct msm_gem_address_space *aspace = kms->base.aspace;
> struct dpu_hw_fmt_layout layout;
> bool layout_valid = false;
> - int ret;
> + int ret, i;
>
> ret = dpu_format_populate_layout(aspace, fb, &layout);
> if (ret)
> @@ -1412,28 +1412,28 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> crtc->base.id, DRM_RECT_ARG(&state->dst),
> &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
>
> - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
> - drm_mode_vrefresh(&crtc->mode),
> - layout_valid ? &layout : NULL);
> -
> - if (r_pipe->sspp) {
> - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt,
> - drm_mode_vrefresh(&crtc->mode),
> - layout_valid ? &layout : NULL);
> + for (i = 0; i < PIPES_PER_STAGE; i++) {
> + if (pstate->pipe_cfg[i].visible && pstate->pipe[i].sspp)
> + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i],
> + &pstate->pipe_cfg[i], fmt,
> + drm_mode_vrefresh(&crtc->mode),
> + layout_valid ? &layout : NULL);
> }
>
> if (pstate->needs_qos_remap)
> pstate->needs_qos_remap = false;
>
> - pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
> - &crtc->mode, pipe_cfg);
> -
> - pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
> -
> - if (r_pipe->sspp) {
> - pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
> + pstate->plane_fetch_bw = 0;
> + pstate->plane_clk = 0;
> + for (i = 0; i < PIPES_PER_STAGE; i++) {
> + pipe_cfg = &pstate->pipe_cfg[i];
> + if (pipe_cfg->visible) {
> + pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt,
> + &crtc->mode, pipe_cfg);
>
> - pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
> + pstate->plane_clk = max(pstate->plane_clk,
> + _dpu_plane_calc_clk(&crtc->mode, pipe_cfg));
> + }
> }
> }
>
> @@ -1441,17 +1441,21 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane)
> {
> struct drm_plane_state *state = plane->state;
> struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
> + struct dpu_sw_pipe *pipe;
> + int i;
>
> - trace_dpu_plane_disable(DRMID(plane), false,
> - pstate->pipe.multirect_mode);
> + for (i = 0; i < PIPES_PER_STAGE; i++) {
> + pipe = &pstate->pipe[i];
> + if (pipe->multirect_index == DPU_SSPP_RECT_1) {
No, the code isn't equivalent.
> + trace_dpu_plane_disable(DRMID(plane), false,
> + pstate->pipe[i - 1].multirect_mode);
>
> - if (r_pipe->sspp) {
> - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> + pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
>
> - if (r_pipe->sspp->ops.setup_multirect)
> - r_pipe->sspp->ops.setup_multirect(r_pipe);
> + if (pipe->sspp && pipe->sspp->ops.setup_multirect)
> + pipe->sspp->ops.setup_multirect(pipe);
> + }
> }
>
> pstate->pending = true;
> @@ -1607,14 +1611,17 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> + int i;
>
> if (!pdpu->is_rt_pipe)
> return;
>
> pm_runtime_get_sync(&dpu_kms->pdev->dev);
> - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable);
> - if (pstate->r_pipe.sspp)
> - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable);
> + for (i = 0; i < PIPES_PER_STAGE; i++) {
> + if (!pstate->pipe_cfg[i].visible)
> + break;
continue, not break.
> + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable);
> + }
> pm_runtime_put_sync(&dpu_kms->pdev->dev);
> }
> #endif
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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