linux-kernel - Re: [PATCH v2 11/11] platform/x86:intel/pmc: Get LPM information for Lunar Lake

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <d270b60b-f136-a520-1703-efa4cbfb0aba@linux.intel.com>
Date: Thu, 29 Aug 2024 15:13:37 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Xi Pardee <xi.pardee@...ux.intel.com>
cc: irenic.rajneesh@...il.com, david.e.box@...ux.intel.com, 
    Hans de Goede <hdegoede@...hat.com>, platform-driver-x86@...r.kernel.org, 
    LKML <linux-kernel@...r.kernel.org>, linux-pm@...r.kernel.org
Subject: Re: [PATCH v2 11/11] platform/x86:intel/pmc: Get LPM information
 for Lunar Lake

On Wed, 28 Aug 2024, Xi Pardee wrote:

> Add support to find and read the requirements from the telemetry
> entries for Lunar Lake platforms.
> 
> Signed-off-by: Xi Pardee <xi.pardee@...ux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/lnl.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c
> index 109b08d43fc8..f5fee9e105e2 100644
> --- a/drivers/platform/x86/intel/pmc/lnl.c
> +++ b/drivers/platform/x86/intel/pmc/lnl.c
> @@ -13,8 +13,13 @@
>  
>  #include "core.h"
>  
> +#define SOCM_LPM_REQ_GUID	0x15099748
> +
> +static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
> +
>  static struct pmc_info lnl_pmc_info_list[] = {
>  	{
> +		.guid	= SOCM_LPM_REQ_GUID,
>  		.devid	= PMC_DEVID_LNL_SOCM,
>  		.map	= &lnl_socm_reg_map,
>  	},
> @@ -536,6 +541,7 @@ const struct pmc_reg_map lnl_socm_reg_map = {
>  	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
>  	.s0ix_blocker_maps = lnl_blk_maps,
>  	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
> +	.lpm_reg_index = LNL_LPM_REG_INDEX,
>  };
>  
>  #define LNL_NPU_PCI_DEV		0x643e
> @@ -561,6 +567,8 @@ static int lnl_resume(struct pmc_dev *pmcdev)
>  
>  int lnl_core_init(struct pmc_dev *pmcdev)
>  {
> +	bool ssram_init = true;
> +	int func = 2;
>  	int ret;
>  	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC];
>  
> @@ -578,6 +586,7 @@ int lnl_core_init(struct pmc_dev *pmcdev)
>  
>  	/* If regbase not assigned, set map and discover using legacy method */
>  	if (ret) {
> +		ssram_init = false;
>  		pmc->map = &lnl_socm_reg_map;
>  		ret = get_primary_reg_base(pmc);
>  		if (ret)
> @@ -586,5 +595,11 @@ int lnl_core_init(struct pmc_dev *pmcdev)
>  
>  	pmc_core_get_low_power_modes(pmcdev);
>  
> +	if (ssram_init)	{
> +		ret = pmc_core_ssram_get_lpm_reqs(pmcdev, func);
> +		if (ret)
> +			return ret;

There's quite much duplication related to this legacy/ssram init in
the per arch core init functions. And some inconsistencies too which
seem incidental such as mtl.c using return directly here.

-- 
 i.