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Message-ID: <20240830133908.2246139-2-quic_mojha@quicinc.com>
Date: Fri, 30 Aug 2024 19:09:08 +0530
From: Mukesh Ojha <quic_mojha@...cinc.com>
To: <conor+dt@...nel.org>, <krzk+dt@...nel.org>, <robh@...nel.org>,
        <konradybcio@...nel.org>, <andersson@...nel.org>, <lee@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, Mukesh Ojha <quic_mojha@...cinc.com>,
        "Elliot
 Berman" <quic_eberman@...cinc.com>
Subject: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Add TCSR halt register space

Enable download mode for sa8775p which can help collect
ramdump for this SoC.

Reviewed-by: Elliot Berman <quic_eberman@...cinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@...cinc.com>
---
Changes in v2:
 - Added R-by tag and rebased it.

 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index e8dbc8d820a6..fa057073ee2d 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -281,6 +281,7 @@ eud_in: endpoint {
 	firmware {
 		scm {
 			compatible = "qcom,scm-sa8775p", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
 			memory-region = <&tz_ffi_mem>;
 		};
 	};
@@ -3072,6 +3073,11 @@ tcsr_mutex: hwlock@...0000 {
 			#hwlock-cells = <1>;
 		};
 
+		tcsr: syscon@...0000 {
+			compatible = "qcom,sa8775p-tcsr", "syscon";
+			reg = <0x0 0x1fc0000 0x0 0x30000>;
+		};
+
 		gpucc: clock-controller@...0000 {
 			compatible = "qcom,sa8775p-gpucc";
 			reg = <0x0 0x03d90000 0x0 0xa000>;
-- 
2.34.1


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