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Message-ID: <20240830152912.9092-1-shimrrashai@gmail.com>
Date: Fri, 30 Aug 2024 10:29:12 -0500
From: Shimrra Shai <shimrrashai@...il.com>
To: shimrrashai@...il.com
Cc: Laurent.pinchart@...asonboard.com,
	aarnoud@...com,
	airlied@...il.com,
	algea.cao@...k-chips.com,
	andrzej.hajda@...el.com,
	andy.yan@...k-chips.com,
	conor+dt@...nel.org,
	cristian.ciocaltea@...labora.com,
	daniel@...ll.ch,
	devicetree@...r.kernel.org,
	dri-devel@...ts.freedesktop.org,
	heiko@...ech.de,
	hjc@...k-chips.com,
	jernej.skrabec@...il.com,
	jonas@...boo.se,
	krzk+dt@...nel.org,
	ldearquer@...il.com,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	linux-rockchip@...ts.infradead.org,
	maarten.lankhorst@...ux.intel.com,
	markyao0591@...il.com,
	mripard@...nel.org,
	neil.armstrong@...aro.org,
	rfoss@...nel.org,
	robh@...nel.org,
	s.hauer@...gutronix.de,
	tzimmermann@...e.de
Subject: [PATCH v5? 6/6] dts: rockchip: add HDMI0 entry for RK3588 and change VO0/1 GRF compatibles

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index b6e4df180..76cb0f7f7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -582,13 +582,13 @@ vop_grf: syscon@...a4000 {
 	};

 	vo0_grf: syscon@...a6000 {
-		compatible = "rockchip,rk3588-vo-grf", "syscon";
+		compatible = "rockchip,rk3588-vo0-grf", "syscon";
 		reg = <0x0 0xfd5a6000 0x0 0x2000>;
 		clocks = <&cru PCLK_VO0GRF>;
 	};

 	vo1_grf: syscon@...a8000 {
-		compatible = "rockchip,rk3588-vo-grf", "syscon";
+		compatible = "rockchip,rk3588-vo1-grf", "syscon";
 		reg = <0x0 0xfd5a8000 0x0 0x100>;
 		clocks = <&cru PCLK_VO1GRF>;
 	};
@@ -1254,6 +1254,46 @@ i2s9_8ch: i2s@...fc000 {
 		status = "disabled";
 	};

+	hdmi0: hdmi@...80000 {
+		compatible = "rockchip,rk3588-dw-hdmi-qp";
+		reg = <0x0 0xfde80000 0x0 0x20000>;
+		clocks = <&cru PCLK_HDMITX0>,
+			 <&cru CLK_HDMITX0_EARC>,
+			 <&cru CLK_HDMITX0_REF>,
+			 <&cru MCLK_I2S5_8CH_TX>,
+			 <&cru CLK_HDMIHDP0>,
+			 <&cru HCLK_VO1>;
+		clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "avp", "cec", "earc", "main", "hpd";
+		phys = <&hdptxphy_hdmi0>;
+		phy-names = "hdmi";
+		power-domains = <&power RK3588_PD_VO1>;
+		resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+		reset-names = "ref", "hdp";
+		rockchip,grf = <&sys_grf>;
+		rockchip,vo1-grf = <&vo1_grf>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi0_in: port@0 {
+				reg = <0>;
+			};
+
+			hdmi0_out: port@1 {
+				reg = <1>;
+			};
+		};
+	};
+
 	qos_gpu_m0: qos@...35000 {
 		compatible = "rockchip,rk3588-qos", "syscon";
 		reg = <0x0 0xfdf35000 0x0 0x20>;

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