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Message-ID: <vsg4izby2zjcdtkwteti6by7sl5rwddzqw32yhnevhobgmy6cg@hx6n7tthwj5l>
Date: Fri, 30 Aug 2024 20:29:44 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Jessica Zhang <quic_jesszhan@...cinc.com>
Cc: Rob Clark <robdclark@...il.com>, quic_abhinavk@...cinc.com,
Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, quic_ebharadw@...cinc.com, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Rob Clark <robdclark@...omium.org>
Subject: Re: [PATCH 16/21] drm/msm/dpu: Program hw_ctl to support CWB
On Thu, Aug 29, 2024 at 01:48:37PM GMT, Jessica Zhang wrote:
> Add support for configuring the CWB pending flush and active bits
Details are appreciated.
Other than that:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>
> Signed-off-by: Jessica Zhang <quic_jesszhan@...cinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 +++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 13 ++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 30 +++++++++++++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 14 +++++++++-
> 4 files changed, 62 insertions(+), 3 deletions(-)
>
--
With best wishes
Dmitry
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